{"title":"混合结构中电流型数模转换器的设计","authors":"Chuen-Yau Chen, Chi-Jung Cheng, Chien-Cheng Yu","doi":"10.1109/NEWCAS.2005.1496715","DOIUrl":null,"url":null,"abstract":"This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"241 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design of current-mode digital-to-analog converter in hybrid architecture\",\"authors\":\"Chuen-Yau Chen, Chi-Jung Cheng, Chien-Cheng Yu\",\"doi\":\"10.1109/NEWCAS.2005.1496715\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.\",\"PeriodicalId\":131387,\"journal\":{\"name\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"volume\":\"241 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2005.1496715\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of current-mode digital-to-analog converter in hybrid architecture
This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.
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