{"title":"一种高效率e类功率放大器功率控制的新拓扑","authors":"M. M. Tabrizi, N. Masoumi, S. Aghnout","doi":"10.1109/NEWCAS.2005.1496744","DOIUrl":null,"url":null,"abstract":"In this paper a new methodology to improve overall efficiency of class E power amplifier is proposed. Power amplifiers are designed to have the maximum efficiency at its highest output power but the efficiency decreases as the output power is reduced. To have more battery life and blocking interference, output power must be controlled due to the distance between the transmitter and the receiver. This new methodology uses optimized circuit topology in power control unit to have small drop in efficiency at low output power. Proposed circuit is simulated with Hspice in 0.25/spl mu/m CMOS technology and ADS lumped model of spiral inductors is used. The results show that the efficiency drop is about 40% when power amplifier is work with its 10% of output power.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A new topology for power control of high efficiency class-E power amplifier\",\"authors\":\"M. M. Tabrizi, N. Masoumi, S. Aghnout\",\"doi\":\"10.1109/NEWCAS.2005.1496744\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new methodology to improve overall efficiency of class E power amplifier is proposed. Power amplifiers are designed to have the maximum efficiency at its highest output power but the efficiency decreases as the output power is reduced. To have more battery life and blocking interference, output power must be controlled due to the distance between the transmitter and the receiver. This new methodology uses optimized circuit topology in power control unit to have small drop in efficiency at low output power. Proposed circuit is simulated with Hspice in 0.25/spl mu/m CMOS technology and ADS lumped model of spiral inductors is used. The results show that the efficiency drop is about 40% when power amplifier is work with its 10% of output power.\",\"PeriodicalId\":131387,\"journal\":{\"name\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2005.1496744\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文提出了一种提高E类功率放大器整体效率的新方法。功率放大器的设计是在其最高输出功率时具有最高效率，但效率随着输出功率的降低而降低。为了延长电池寿命和阻挡干扰，必须根据发射器和接收器之间的距离控制输出功率。该方法在功率控制单元中采用优化的电路拓扑结构，在低输出功率下具有较小的效率下降。利用Hspice在0.25/spl μ m CMOS技术下对所提出的电路进行了仿真，并采用了螺旋电感的ADS集总模型。结果表明，当功率放大器以10%的输出功率工作时，效率下降约40%。
A new topology for power control of high efficiency class-E power amplifier
In this paper a new methodology to improve overall efficiency of class E power amplifier is proposed. Power amplifiers are designed to have the maximum efficiency at its highest output power but the efficiency decreases as the output power is reduced. To have more battery life and blocking interference, output power must be controlled due to the distance between the transmitter and the receiver. This new methodology uses optimized circuit topology in power control unit to have small drop in efficiency at low output power. Proposed circuit is simulated with Hspice in 0.25/spl mu/m CMOS technology and ADS lumped model of spiral inductors is used. The results show that the efficiency drop is about 40% when power amplifier is work with its 10% of output power.
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