{"title":"用于高速背板数据通信的6.25Gb/s流水线式半速率决策反馈均衡器","authors":"J. Chen, T. Kwasniewski","doi":"10.1109/NEWCAS.2005.1496689","DOIUrl":null,"url":null,"abstract":"A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18/spl mu/m CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34\" FR4 backplane. The total power consumption is 8.91 mW with a 1.8V supply.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications\",\"authors\":\"J. Chen, T. Kwasniewski\",\"doi\":\"10.1109/NEWCAS.2005.1496689\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18/spl mu/m CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34\\\" FR4 backplane. The total power consumption is 8.91 mW with a 1.8V supply.\",\"PeriodicalId\":131387,\"journal\":{\"name\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2005.1496689\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications
A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18/spl mu/m CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34" FR4 backplane. The total power consumption is 8.91 mW with a 1.8V supply.
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