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Adaptive harmonic balance analysis of oscillators using multiple time scales 多时间尺度振荡器自适应谐波平衡分析
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/newcas.2005.1496738
Lei Zhu, C. Christoffersen
{"title":"Adaptive harmonic balance analysis of oscillators using multiple time scales","authors":"Lei Zhu, C. Christoffersen","doi":"10.1109/newcas.2005.1496738","DOIUrl":"https://doi.org/10.1109/newcas.2005.1496738","url":null,"abstract":"A harmonic balance (HB) method to analyze the steady-state response of free-running oscillators is proposed. It does not require a good initial guess of the oscillation frequency and exploits the frequency-domain latency of circuits by using a different number of harmonics in each variable. For the first time the warped multi-time partial differential equation approach is used to simultaneously bring the circuit state to the region of convergence of the HB analysis and determine the optimum number of harmonics required at each node in the circuit. The analysis of a LC-tuned bipolar oscillator is used to demonstrate the proposed method.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127217242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Java-enabled low cost RF vector network analyzer 支持java的低成本RF矢量网络分析仪
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496681
B. De Mulder, K. Van Renterghem, E. De Backer, P. Suanet, J. Vandewege
{"title":"Java-enabled low cost RF vector network analyzer","authors":"B. De Mulder, K. Van Renterghem, E. De Backer, P. Suanet, J. Vandewege","doi":"10.1109/NEWCAS.2005.1496681","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496681","url":null,"abstract":"This paper describes a compact, low cost, low power vector network analyzer. The instrument's measurement range spans from 300 kHz up to 1500 MHz. The design was conceived to make the instrument generic and suited for many application areas. The instrument runs a local Web server, hosting a Java applet that contains application specific data processing software. We present the system architecture, discuss sub-block performance and propose some possible applications.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mapping multiplexers onto hard multipliers in FPGAs 将多路复用器映射到fpga中的硬乘法器上
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496692
P. Jamieson, Jonathan Rose
{"title":"Mapping multiplexers onto hard multipliers in FPGAs","authors":"P. Jamieson, Jonathan Rose","doi":"10.1109/NEWCAS.2005.1496692","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496692","url":null,"abstract":"Modern FPGAs now contain a selection of \"hard\" digital structures such as memory blocks and multipliers (Altera, 2003, Xilinx, 2003, QuickLogic, 2003, Actel, Lattice, 2004) in addition to the usual \"soft\" programmable logic typically consisting of lookup tables (LUTs) and flip-flops. These hard structures are a major benefit (in area and speed) for those applications that need them, but are completely wasted if an application circuit docs not require them. Finding other ways to use these structures will benefit these applications. In this paper, the authors presented a technique to map multiplexers to unused hard multipliers on an FPGA. An RTL synthesis tool flow that implements this technique over a set of benchmarks was created. While some circuits see no reduction in LUT count at all, others show meaningful improvements ranging from 10% to 70%. On average across the whole set of circuits the technique achieves a 7.3% reduction on the number of LUTs used. In some cases, however, the operating frequency of the circuit is reduced significantly.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134381195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Pull-in voltage calculations for MEMS sensors with cantilevered beams 悬臂梁MEMS传感器的拉入电压计算
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496695
S. Chowdhury, M. Ahmadi, W. Miller
{"title":"Pull-in voltage calculations for MEMS sensors with cantilevered beams","authors":"S. Chowdhury, M. Ahmadi, W. Miller","doi":"10.1109/NEWCAS.2005.1496695","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496695","url":null,"abstract":"MEMS sensors, such as acoustic, noise and vibration transducers often employ a diaphragm or cantilevered structure as part of a variable capacitance sensor geometry. A bias voltage is necessary to ensure a linear force-capacitance range of operation. The calculation of the pull-in voltage whereby the sensing structure collapses due to electrostatic forces is an important design requirement. A linearized, uniform approximate model of the nonlinear electrostatic pressure has been developed and used in conjunction with the load deflection model of a MEMS cantilever beam under uniform pressure to develop a highly accurate model to calculate the pull-in voltage. The new model improves sensor design methodology by evaluating the pull-in voltage for a cantilever beam with a maximum deviation of less than 1% from the finite element analysis results for wide beams and for narrow beams with extreme fringing fields.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121028808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Model driven engineering for SoC co-design SoC协同设计的模型驱动工程
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496724
J. Dekeyser, Pierre Boulet, P. Marquet, S. Meftali
{"title":"Model driven engineering for SoC co-design","authors":"J. Dekeyser, Pierre Boulet, P. Marquet, S. Meftali","doi":"10.1109/NEWCAS.2005.1496724","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496724","url":null,"abstract":"SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to SystemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127550387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
New designs of signed multipliers 符号乘法器的新设计
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496746
R. Mudassir, H. El-Razouk, Z. Abid
{"title":"New designs of signed multipliers","authors":"R. Mudassir, H. El-Razouk, Z. Abid","doi":"10.1109/NEWCAS.2005.1496746","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496746","url":null,"abstract":"Two new architectures for signed multiplication for array and tree topologies are presented. The signed array multiplier is based on the new low power high speed adders, and achieves 15% and 30% reduction in time-delay and power consumption compared to Baugh Wooley's. The proposed tree multiplier incorporates two new low-power (4:2) compressors, capable of handling negative weights, and achieves 10% and 19% reduction in time-delay and power consumption compared to Wallace multiplier.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Logical path delay distribution and transistor sizing 逻辑路径延迟分布和晶体管尺寸
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496701
A. Kabbani, D. Al-Khalili, A. Al-Khalili
{"title":"Logical path delay distribution and transistor sizing","authors":"A. Kabbani, D. Al-Khalili, A. Al-Khalili","doi":"10.1109/NEWCAS.2005.1496701","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496701","url":null,"abstract":"The merits of high performance design are high speed, low power consumption, and small silicon area. Area optimization could be achieved at different levels of the design abstraction. In this paper area-delay optimization technique that depends on library-free synthesis and transistor sizing is presented. This technique can be used to optimize the path delay or to minimize the path area for a specific given required time. It is generated depending on the CMOS inverter delay model, modified logical effort (MLE) model [A. Kabbani, D. Al-Khalili, and A. J. Al-Khalili (2004)] and the CMOS gate transition time model [A. Kabbani (2004)]. The proposed technique achieves better performance as compared to Synopsys's design compiler. For a given required time, the presented technique saves on area-delay product by about 50% on the average.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"62 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130626898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Balancing scratchpad and cache in embedded systems for power and speed performance 在嵌入式系统中平衡刮擦板和缓存的功率和速度性能
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496685
J. Pfrimmer, K. Li, D. Rakhmatov
{"title":"Balancing scratchpad and cache in embedded systems for power and speed performance","authors":"J. Pfrimmer, K. Li, D. Rakhmatov","doi":"10.1109/NEWCAS.2005.1496685","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496685","url":null,"abstract":"Scratchpad memories can be an effective alternative to cache in embedded applications, but have drawbacks of their own. The most effective memory configuration for any given application may be one which combines cache and scratchpad on a single chip, however manufacturing expenses limit the amount of total on-chip memory for any SoC. Given an area budget for on-chip memory, this paper proposes a methodology by which a designer can determine the optimal mix of scratchpad and cache for an application, and ensure that the scratchpad is used effectively with improvement in system power consumption and execution speed.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128089937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high-speed driver for current-programmed active-matrix OLED displays 用于电流编程有源矩阵OLED显示器的高速驱动器
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496757
S. Jafarabadiashtiani, P. Servati, A. Nathan
{"title":"A high-speed driver for current-programmed active-matrix OLED displays","authors":"S. Jafarabadiashtiani, P. Servati, A. Nathan","doi":"10.1109/NEWCAS.2005.1496757","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496757","url":null,"abstract":"This paper proposes a new driving technique for improving settling time in current-programmed active-matrix organic light-emitting diode (AMOLED) pixel circuits. Here, a current feedback along with a second generation current conveyer is employed as the driver to cancel the effect of parasitic line capacitances. Circuit-level simulation using a high-voltage CMOS process for external driver and a VerligA model for amorphous silicon thin film transistors shows more than 8 times reduction in programming time of a typical current programmed pixel circuit for programming current of 100nA.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129325698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A practical approach to phase noise estimation in reflection microwave oscillators 一种实用的反射微波振荡器相位噪声估计方法
The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI: 10.1109/NEWCAS.2005.1496741
M. Stadler, W. Bachtold
{"title":"A practical approach to phase noise estimation in reflection microwave oscillators","authors":"M. Stadler, W. Bachtold","doi":"10.1109/NEWCAS.2005.1496741","DOIUrl":"https://doi.org/10.1109/NEWCAS.2005.1496741","url":null,"abstract":"This paper describes a procedure that enables the designer to estimate phase noise in a reflection oscillator to a high degree of accuracy, using only large-signal S-parameter measurements and basic knowledge of noise processes in bipolar transistors. No detailed knowledge of the large signal transistor model and no large signal simulation tools are used in order to keep the practical value of this method as high as possible. The validity of this approach is demonstrated experimentally, showing very close agreement between measurements and theory.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130237063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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