将多路复用器映射到fpga中的硬乘法器上

P. Jamieson, Jonathan Rose
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引用次数: 15

摘要

现代fpga现在除了通常的“软”可编程逻辑(通常由查找表(lut)和触发器组成)之外,还包含一些“硬”数字结构,如存储器块和乘法器(Altera, 2003年,Xilinx, 2003年,QuickLogic, 2003年,Actel, Lattice, 2004年)。对于那些需要它们的应用程序来说,这些硬结构是一个主要的优势(在面积和速度上),但如果应用电路不需要它们,则完全是浪费。寻找使用这些结构的其他方法将有利于这些应用程序。在本文中,作者提出了一种将多路复用器映射到FPGA上未使用的硬乘法器的技术。创建了一个RTL综合工具流,它在一组基准测试上实现了该技术。虽然一些电路根本没有看到LUT计数的减少,但其他电路显示出从10%到70%不等的有意义的改进。在整个电路中,该技术平均减少了7.3%的lut使用数量。然而,在某些情况下,电路的工作频率显著降低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mapping multiplexers onto hard multipliers in FPGAs
Modern FPGAs now contain a selection of "hard" digital structures such as memory blocks and multipliers (Altera, 2003, Xilinx, 2003, QuickLogic, 2003, Actel, Lattice, 2004) in addition to the usual "soft" programmable logic typically consisting of lookup tables (LUTs) and flip-flops. These hard structures are a major benefit (in area and speed) for those applications that need them, but are completely wasted if an application circuit docs not require them. Finding other ways to use these structures will benefit these applications. In this paper, the authors presented a technique to map multiplexers to unused hard multipliers on an FPGA. An RTL synthesis tool flow that implements this technique over a set of benchmarks was created. While some circuits see no reduction in LUT count at all, others show meaningful improvements ranging from 10% to 70%. On average across the whole set of circuits the technique achieves a 7.3% reduction on the number of LUTs used. In some cases, however, the operating frequency of the circuit is reduced significantly.
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