Balancing scratchpad and cache in embedded systems for power and speed performance

Abstract

Scratchpad memories can be an effective alternative to cache in embedded applications, but have drawbacks of their own. The most effective memory configuration for any given application may be one which combines cache and scratchpad on a single chip, however manufacturing expenses limit the amount of total on-chip memory for any SoC. Given an area budget for on-chip memory, this paper proposes a methodology by which a designer can determine the optimal mix of scratchpad and cache for an application, and ensure that the scratchpad is used effectively with improvement in system power consumption and execution speed.