New designs of signed multipliers

Abstract

Two new architectures for signed multiplication for array and tree topologies are presented. The signed array multiplier is based on the new low power high speed adders, and achieves 15% and 30% reduction in time-delay and power consumption compared to Baugh Wooley's. The proposed tree multiplier incorporates two new low-power (4:2) compressors, capable of handling negative weights, and achieves 10% and 19% reduction in time-delay and power consumption compared to Wallace multiplier.