{"title":"2ghz AMBA AHB总线的电路技术","authors":"A. Landry, Y. Savaria, M. Nekili","doi":"10.1109/NEWCAS.2005.1496755","DOIUrl":null,"url":null,"abstract":"This paper explores various circuit techniques applicable to design a high-performance full-custom AMBA advanced high-speed bus (AHB). The authors have demonstrated that clock frequencies in excess of 2 GHz are feasible with a 180nm CMOS process from TSMC. This result is obtained by means of proper clocking strategy, aggressive transistor sizing, efficient logic style, and meticulous layout techniques. Feasibility of the proposed bus is supported with details of a run-time reprogrammable VLIW AHB arbiter. Circuit simulations show that this core operates up to 3 GHz.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Circuit techniques for a 2 GHz AMBA AHB bus\",\"authors\":\"A. Landry, Y. Savaria, M. Nekili\",\"doi\":\"10.1109/NEWCAS.2005.1496755\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores various circuit techniques applicable to design a high-performance full-custom AMBA advanced high-speed bus (AHB). The authors have demonstrated that clock frequencies in excess of 2 GHz are feasible with a 180nm CMOS process from TSMC. This result is obtained by means of proper clocking strategy, aggressive transistor sizing, efficient logic style, and meticulous layout techniques. Feasibility of the proposed bus is supported with details of a run-time reprogrammable VLIW AHB arbiter. Circuit simulations show that this core operates up to 3 GHz.\",\"PeriodicalId\":131387,\"journal\":{\"name\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2005.1496755\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper explores various circuit techniques applicable to design a high-performance full-custom AMBA advanced high-speed bus (AHB). The authors have demonstrated that clock frequencies in excess of 2 GHz are feasible with a 180nm CMOS process from TSMC. This result is obtained by means of proper clocking strategy, aggressive transistor sizing, efficient logic style, and meticulous layout techniques. Feasibility of the proposed bus is supported with details of a run-time reprogrammable VLIW AHB arbiter. Circuit simulations show that this core operates up to 3 GHz.
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