Circuit techniques for a 2 GHz AMBA AHB bus

Abstract

This paper explores various circuit techniques applicable to design a high-performance full-custom AMBA advanced high-speed bus (AHB). The authors have demonstrated that clock frequencies in excess of 2 GHz are feasible with a 180nm CMOS process from TSMC. This result is obtained by means of proper clocking strategy, aggressive transistor sizing, efficient logic style, and meticulous layout techniques. Feasibility of the proposed bus is supported with details of a run-time reprogrammable VLIW AHB arbiter. Circuit simulations show that this core operates up to 3 GHz.