A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed track-and-hold (T/H), a novel one-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18/spl mu/m CMOS occupies an area of 977/spl mu/m /spl times/ 1040/spl mu/m and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.