VLSI implementation of bit-parallel word-serial multiplier in GF(2/sup 233/)

Abstract

A bit-parallel word-serial (BPWS) finite field multiplier in GF(2/sup 233/) is proposed in this paper. The complexities are lower than or comparable to those of the previous similar proposals. A VLSI implementation of the BPWS multiplier combined with a bit-parallel squarer is also presented. The fabricated ASIC chip can be used as the finite field arithmetic module on an elliptic curve technique based cryptographic accelerator board and the proposed VLSI design could also be utilized as a design IP core for fast implementation of a cryptographic processor or smart card.