A 1.6 GHz digital DLL for optical clock distribution

This paper describes the circuit architecture of a digital delay locked loop (DDL)-based clock generator for optical clock distribution. DLL-based clock generators have several advantages over conventional phase lock loop (PLL)-based clock generators, namely their design simplicity and their transferability among CMOS processes. Its architecture is based on a digital phase detector which controls a 6-bit up-down counter. The counter digital output is then converted into an analog signal that generates the control voltage of a delay line. This design is aimed for an on-chip optical clock distribution network where optical receivers are used to transmit the global optical clock signal to local DLL-based clock generators. Hence a frequency multiplier connected at the output of the voltage-controlled delay line allows for a global optical clock operating at lower frequencies which reduces the performance requirements of the optical receiver. Simulation results of the DLL designed in a 0.18/spl mu/m CMOS process are presented. The circuit is able to generate a local clock signal at frequencies ranging from 1.32 to 1.6 GHz.