基于乘数器的二进制递增/递减数

The 3rd International IEEE-NEWCAS Conference, 2005. Pub Date : 2005-06-19 DOI:10.1109/NEWCAS.2005.1496662

Shaoqiang Bi, Wei Wang, A. Al-Khalili

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引用次数: 15

摘要

本文提出了一种新的基于多路复用器(MUX)的递增/递减器。对于有符号和无符号的情况，所提出的设计在速度和硬件复杂性方面都比基于加法器的设计更有效。FPGA实现对比表明，该设计可将面积和延迟减少近40%。基于mux的设计功耗比基于进位传播加法器(CPA)的设计功耗低近35%。

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Multiplexer-based binary incrementer/decrementers

In this paper, novel multiplexer (MUX)-based incrementer/decrementers are proposed. The proposed designs are more efficient in terms of speed and hardware complexity compared to the adder-based ones for both signed and unsigned cases. A FPGA implementation comparison shows that the proposed design reduces both area and delay close to 40%. The power consumed by the MUX-based design is almost 35% less than that of the carry propagation adder (CPA)-based design.

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来源期刊

The 3rd International IEEE-NEWCAS Conference, 2005.

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