A 130nm partially depleted SOI technology menu for low-power applications

Abstract

In this paper, we present a technology-based menu where the target performance and power consumption are achieved by selecting a given design point (supply voltage, normal V/sub T/, low V/sub T/ and DTMOS transistors) according to a given application. Through analyses made at synthesis and silicon measurements levels, it is shown that the best results are obtained by optimizing the SOI technology for the targeted power supply voltage. At the nominal 1.2V supply voltage, this is achieved by setting a higher threshold voltage V/sub T/ to limit the cut-off currents. The power gains are in the order of 25% to 30% for the same performance. To further reduce the power dissipation, targeting the ultra-low-voltage range (0.5V) is very attractive when performance is not an issue. Using low-V/sub T/ SOI transistors allows significant gains in terms of speed and power. The power-delay product of a 16-bit multiplier is improved by a 2.4 factor.