{"title":"A 3-10 GHz 0.13/spl mu/m CMOS body effect reuse LNA for UWB applications","authors":"T. Taris, J. Bégueret, H. Lapuyade, Y. Deval","doi":"10.1109/NEWCAS.2005.1496710","DOIUrl":null,"url":null,"abstract":"Focusing on low noise amplifier (LNA) which is one of the main building blocks in UWB receiver, this paper highlights the RF design constraints induced by the implementation of this key cell in a standard CMOS technology. An UWB input matching theory is proposed achieving a -13 dB S/sub 11/ from 2.8 to 10.5 GHz while the LNA is in a reuse implementation topology. Indeed this UWB LNA provides a 13 dB quasi-flat band gain from 2.8 to 12.8 GHz with a 4.2 dB average noise figure (NF). Operating under 1 V, this circuit addresses the low voltage constrain of modern CMOS technology whose the traditional cascade topology cannot to be compelled.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496710","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Focusing on low noise amplifier (LNA) which is one of the main building blocks in UWB receiver, this paper highlights the RF design constraints induced by the implementation of this key cell in a standard CMOS technology. An UWB input matching theory is proposed achieving a -13 dB S/sub 11/ from 2.8 to 10.5 GHz while the LNA is in a reuse implementation topology. Indeed this UWB LNA provides a 13 dB quasi-flat band gain from 2.8 to 12.8 GHz with a 4.2 dB average noise figure (NF). Operating under 1 V, this circuit addresses the low voltage constrain of modern CMOS technology whose the traditional cascade topology cannot to be compelled.