An optimized systolic array architecture for full search block matching algorithm and its implementation on FPGA chips

Abstract

In this paper, an optimized systolic array architecture for FSBMA is presented. This array architecture is implemented by RTL-level VHDL. It is synthesized for two FPGA families, Xilinx Spartan II and Xilinx Virtex II and the results for area occupation and maximum operating frequency are presented. The results show this array architecture is suitable for real-time video encoding systems with minimum hardware utilization and high performance.