Parallel hashing memories: an alternative to content addressable memories

Abstract

Content addressable memories, or CAMs, are commonly used in applications requiring high speed access to data sets. This technology allows data items to be accessed in constant time based on content rather than on address. Unfortunately, this technology has several drawbacks: it occupies more die area per bit, costs more, dissipates more power, and has a higher latency. This article proposes an alternative to CAM technology based on a parallel hashing architecture. Simulations show that CAM performances can be matched and even surpassed while reducing cost and power consumption. The tradeoffs that exist between performance and cost are explored in the paper.