A low-power high-performance digital circuit for deep submicron technologies

This paper presents a novel digital circuit design methodology that can support high-performance and low-power applications. In this method, reusing past internal voltages, signals are charged to Vdd/2 during the pre-charge cycle, so that the voltage of a signal is changed by just Vdd/2 during the evaluation cycle, resulting in a significant reduction in power consumption and propagation delay. The simulation results performed in 0.18/spl mu/m CMOS technology, demonstrate that the new circuit has three times improvement in terms of propagation delay in comparison to the equivalent domino dynamic logics. More importantly, its power consumption is 2.4 times less than that of the domino logics counterpart.