{"title":"异步BCJR/MAP卷积信道解码器数字设计流程的可行性","authors":"K. Perta, K. Tepe","doi":"10.1109/NEWCAS.2005.1496735","DOIUrl":null,"url":null,"abstract":"The current technology in the design of BCJR or MAP decoders utilizes standard electronic design and automation (EDA) tools in the synchronous paradigm. The BCJR/MAP decoder has gained large scale importance in convolutional coding, especially with its importance in turbo codes. This paper examines the feasibility and benefits of an asynchronous design of a BCJR/MAP decoder. A comparison against other gate level decoders is examined and promising results are shown.","PeriodicalId":131387,"journal":{"name":"The 3rd International IEEE-NEWCAS Conference, 2005.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Feasibility of a digital design flow of an asynchronous BCJR/MAP convolutional channel decoder\",\"authors\":\"K. Perta, K. Tepe\",\"doi\":\"10.1109/NEWCAS.2005.1496735\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The current technology in the design of BCJR or MAP decoders utilizes standard electronic design and automation (EDA) tools in the synchronous paradigm. The BCJR/MAP decoder has gained large scale importance in convolutional coding, especially with its importance in turbo codes. This paper examines the feasibility and benefits of an asynchronous design of a BCJR/MAP decoder. A comparison against other gate level decoders is examined and promising results are shown.\",\"PeriodicalId\":131387,\"journal\":{\"name\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd International IEEE-NEWCAS Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2005.1496735\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd International IEEE-NEWCAS Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2005.1496735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Feasibility of a digital design flow of an asynchronous BCJR/MAP convolutional channel decoder
The current technology in the design of BCJR or MAP decoders utilizes standard electronic design and automation (EDA) tools in the synchronous paradigm. The BCJR/MAP decoder has gained large scale importance in convolutional coding, especially with its importance in turbo codes. This paper examines the feasibility and benefits of an asynchronous design of a BCJR/MAP decoder. A comparison against other gate level decoders is examined and promising results are shown.