Effect of statistical clock skew variations on chip timing yield

Abstract

Integrated circuit design with sub-100nm technology requires closer attention to the effect of process variations on circuit timing. In a previous work, we had developed a method of statistical timing analysis in which the effect of process variations on circuit timing is assessed, given a generic logic path in a target design technology. In this work, we extend that previous work in an important way by incorporating into the analysis the effect of clock skew. The resulting model captures both die-to-die and within-die process variations, in both logic and clock paths, it handles within-die correlation using principal component analysis, and it leads to an expression for the resulting timing yield. Among other uses, this allows one to compute how much reduction one will see in the timing yield, for a given clock skew variance.