ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)最新文献

A PAM4 Dielectric Waveguide Link in 28 nm CMOS 28纳米CMOS中的PAM4介电波导链路

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567741

Kristof Dens, Joren Vaes, Simon Ooms, M. Wagner, P. Reynaert

引用次数: 13

Electronic-Photonic Cryogenic Egress Link 电子-光子低温出口链接

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567813

Bozhi Yin, H. Gevorgyan, Deniz Onural, A. Khilo, M. Popović, V. Stojanović

引用次数: 2

A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS 一个22-31 GHz双向5G收发器前端在28纳米CMOS

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567832

D. Manente, F. Quadrelli, F. Padovan, M. Bassi, A. Mazzanti, A. Bevilacqua

引用次数: 3

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs 一种保护存储在安全ram中的敏感数据的近瞬时非侵入性擦除设计技术

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567885

J. Noel, Manuel Pezzin, J. Christmann, Lorenzo Ciampolini, Mikael Le Coadou, Mariam Diallo, Florent Lepin, Benjamin Blampey, Simone Bacles-Min, Romain Wacquez, Mikael Le

{"title":"A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs","authors":"J. Noel, Manuel Pezzin, J. Christmann, Lorenzo Ciampolini, Mikael Le Coadou, Mariam Diallo, Florent Lepin, Benjamin Blampey, Simone Bacles-Min, Romain Wacquez, Mikael Le","doi":"10.1109/ESSCIRC53450.2021.9567885","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567885","url":null,"abstract":"On-chip memories, and in particular SRAMs, are among the most critical components in terms of data security because they might contain sensitive data such as secret keys. Whenever a tampering event is detected, one should be able to erase efficiently and rapidly the full content of a memory holding such sensitive data, but current solutions based on simple power-off lead to very long erasure times. In this paper, we present a non-invasive design technique based on an innovative mechanism to remove electric charges from SRAM bitcells still powered on, before refreshing them with a new content not correlated with the previous one. The particularity of this novel hardware countermeasure is to be natively compatible with any SRAM circuit designed from pushed-rule foundry bitcells. We have designed and characterized an 8kB SRAM in 22nm FD-SOI process technology exploiting the proposed security strategy demonstrating an erase operation accomplished in the nanosecond time scale (versus 295µs with the conventional power-off solution) at the cost of an additional area of less than 5%. We have also shown that our solution is more efficient than a solution without prior erasure consisting in writing identical data to all memory addresses in a single clock cycle (1 ns). The use of the latter drops the ratio of zeroized addresses at 92 %, while increasing the operating energy consumption by 2.1x under nominal operating conditions.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges 采用稳健的2T2R阻性RAM桥的二值化神经网络的低开销实现

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567742

M. Ezzadeen, A. Majumdar, M. Bocquet, B. Giraud, J. Noël, F. Andrieu, D. Querlioz, J. Portal

{"title":"Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges","authors":"M. Ezzadeen, A. Majumdar, M. Bocquet, B. Giraud, J. Noël, F. Andrieu, D. Querlioz, J. Portal","doi":"10.1109/ESSCIRC53450.2021.9567742","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567742","url":null,"abstract":"The energy consumption associated with data movement between memory and processing units is the main roadblock for the massive deployment of edge Artificial Intelligence. To overcome this challenge, Binarized Neural Networks (BNN) coupled with RRAM-based in- or near-memory computing constitute an appealing solution. However, proposals from the literature tend to involve significant periphery circuit overheads. In this work, we propose and demonstrate experimentally, on a fabricated hybrid CMOS-RRAM integrated circuit, a robust in-memory XOR operation based on a 2 $T$ 2R cell used in a resistive bridge manner. With this architecture, the RRAM read operation and the BNN multiplication operation can be achieved simultaneously, requiring only inverters connected to each Source Line of the memory array, and the BNN POPCOUNT operation can be realized with an analog capacitive neuron. Based on our measurements and extensive Monte Carlo simulations, we validate that this approach is suitable for large neurons with a low error rate (3.12% of error considering the full range of POPCOUNT values). Based on the circuit simulation results, we highlight the resilience of this approach at the network level, with a minimal accuracy degradation on the MNIST (0.07%) and CIFAR-10 (0.35%) tasks with regards to software solutions.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128376607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A 60 GHz QDCO with 11 GHz Seamless Tuning for Low-Power FMCW Radars in 22-nm FDSOI 用于22nm FDSOI低功耗FMCW雷达的60ghz QDCO和11ghz无缝调谐

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567787

F. Chicco, Sammy Cerida Rengifo, E. Roux, C. Enz

引用次数: 0

Electric-field controlled spin transport in bilayer CrI3 电场控制双层CrI3的自旋输运

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567800

D. Marian, D. Soriano, E. G. Marín, G. Iannaccone, G. Fiori

引用次数: 0

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS 采用分数间隔预强调和波特间隔去强调的4分导混合FFE的14vppd 64gb /s PAM-4发射机

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567818

Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu

引用次数: 2

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator 200-GS/s ADC前端采用25%占空比正交时钟发生器

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567791

Naftali Weiss, G. Cooke, P. Schvan, P. Chevalier, A. Cathelin, S. Voinigescu

引用次数: 2

Fully integrated reflector-based analog predistortion for Ku-band Power Amplifiers Linearization 基于全集成反射器的ku波段功率放大器线性化模拟预失真

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567737

N. Deltimple, Potereau Manuel, Ghiotto Anthony

引用次数: 2