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ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)最新文献

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7.5nJ/inference CMOS Echo State Network for Coronary Heart Disease prediction 7.5nJ/inference CMOS回波状态网络冠心病预测
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567753
S. T. Chandrasekaran, I. Banerjee, A. Sanyal
{"title":"7.5nJ/inference CMOS Echo State Network for Coronary Heart Disease prediction","authors":"S. T. Chandrasekaran, I. Banerjee, A. Sanyal","doi":"10.1109/ESSCIRC53450.2021.9567753","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567753","url":null,"abstract":"This work presents the first on-chip, mixed-signal echo state network (ESN) for early prediction of heart disease. The ESN comprises an input layer, a non-linear projection (NP) layer, and an output layer. Only the output layer of the ESN requires training. The input layer weights are time-invariant and drawn from a static binary random distribution. Thus, the proposed ESN has significantly lower trainable parameters compared to other non-linear neural networks used for similar prediction tasks. A 65nm prototype is validated with the Cleveland Heart Disease (CHD) dataset. The ESN achieves a mean accuracy of 84.6% over 5 test chips while consuming 7.5nJ energy/inference.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130480005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW CMOS A/D转换器的系统设计教程:以2ghz RBW的10b500ms /s SAR ADC为例
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567842
T. Iizuka, Hao Xu, A. Abidi
{"title":"A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW","authors":"T. Iizuka, Hao Xu, A. Abidi","doi":"10.1109/ESSCIRC53450.2021.9567842","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567842","url":null,"abstract":"This paper presents a systematic design framework for ADC optimization. Our emphasis is on a robust design that is highly repeatable, which is driven by a deep understanding of the behavior of circuit building blocks. A 10 b 500 MS/s single-channel SAR ADC designed in this framework displays uniform performance for inputs up to 2 GHz at state-of-the-art FoM, which demonstrates the power of design based on analytical expressions.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References 具有片上写验证和偏移抵消ADC参考的40nm RRAM内存宏计算
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567844
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
{"title":"A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References","authors":"Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu","doi":"10.1109/ESSCIRC53450.2021.9567844","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567844","url":null,"abstract":"Resistive random access memory (RRAM) based compute-in-memory (CIM) has shown great potentials for deep neural network (DNN) inference. Prior works generally used off-chip write-verify scheme to tighten the RRAM resistance distribution and used off-chip analog-to-digital converter (ADC) references to fine-tune partial sum quantization edges. Though off-chip techniques are viable for testing purposes, they are unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate offsets induced by process variation to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W for 1×1b MAC operations on VGG-8 network.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116524975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link 0.37 pj /b/dB PAM-4发射机和自适应接收机与固定数据和阈值水平的12米汽车摄像头链路
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567857
Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, H. Ko, Woo-Seok Choi, D. Jeong
{"title":"0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link","authors":"Woonghee Lee, Minkyo Shim, Yunhee Lee, Heejin Yang, H. Ko, Woo-Seok Choi, D. Jeong","doi":"10.1109/ESSCIRC53450.2021.9567857","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567857","url":null,"abstract":"This paper presents a transmitter and an adaptive receiver for the next-generation automotive camera link with four-level pulse amplitude modulation (PAM-4) signaling. The PAM-4 transmitter utilizes push-pull current drivers and a 3-tap feed-forward equalizer to improve impedance matching and eye margin, respectively. In order to cancel the sampler offset for a lower bit error rate (BER), instead of adjusting data and threshold levels, the gain of a programmable gain amplifier is adjusted adaptively under fixed data and threshold levels. The transmitter delivers 8-Gb/s PAM-4 signal to the adaptive receiver through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The prototype chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/bit/dB.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124010750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 253–280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS 一种采用40纳米CMOS、峰值输出功率为-3.5 dBm的253-280 GHz宽调谐范围压控振荡器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567849
Surajit Kumar Nath, Junghwan Yoo, J. Rieh, Daekeun Yoon
{"title":"A 253–280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS","authors":"Surajit Kumar Nath, Junghwan Yoo, J. Rieh, Daekeun Yoon","doi":"10.1109/ESSCIRC53450.2021.9567849","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567849","url":null,"abstract":"This paper presents a wide tuning range push-push voltage-controlled oscillator (VCO) at the sub-THz frequency bands. With the introduction of a novel capacitive splitting feedback (CSF) technique and tunable source degeneration (TSD) network, the proposed VCO can simultaneously archive a wide tuning range while maintaining a high output power. The CSF technique improves the oscillation frequency by reducing the effective transistor capacitances, and a wide tuning range is achieved through the TSD network without employing varactors. The proposed VCO is fabricated in a 40-nm digital CMOS process. It shows a -3.5 dBm peak output power with 1.35% DC-to-RF efficiency and a wide tuning range of 10.16% at a center frequency of 267.2 GHz.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124021866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
ESSCIRC 2021 Table of Contents ESSCIRC 2021目录
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/esscirc53450.2021.9567886
{"title":"ESSCIRC 2021 Table of Contents","authors":"","doi":"10.1109/esscirc53450.2021.9567886","DOIUrl":"https://doi.org/10.1109/esscirc53450.2021.9567886","url":null,"abstract":"","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125346535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS 一个9.08 enob10b 400MS/s subanging SAR ADC，带有40nm CMOS的子集CDAC和PDAS
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567859
Q. Yu, Xiong Zhou, Kefeng Hu, Zijian Huang, Haiwen Chen, Xin Si, Jinda Yang, Qiang Li
{"title":"A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS","authors":"Q. Yu, Xiong Zhou, Kefeng Hu, Zijian Huang, Haiwen Chen, Xin Si, Jinda Yang, Qiang Li","doi":"10.1109/ESSCIRC53450.2021.9567859","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567859","url":null,"abstract":"In this work, a 10b 400MS/s single-channel SAR ADC is reported. Without an auxiliary sub-ADC, a subranging architecture is proposed, where only one comparator is used with the subsetted capacitive DAC (CDAC), eliminating the mismatch of comparators and saving area. For the subranging process, a partial detect-and-skip (PDAS) switching scheme is proposed, which improves both power efficiency and linearity without delay overhead. In addition, the dynamic logic circuits, including dynamic asynchronous loop (DAL) and dynamic SAR logic (DSL), are improved to reduce the power and logic propagation delay. Fabricated in a 40 nm CMOS process, this single-channel prototype operates at an enhanced sampling rate of 400 MS/s. At Nyquist, 56.4 dB SNDR and 73.1 dB SFDR are achieved. The ADC draws 3.46mW from a single 1.2V supply, leading to a FoMW of 16.0fJ/ conversion-step.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Architecting the Human Intranet 构建人类内部网
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567774
J. Rabaey, A. Arias, Rikky Muller
{"title":"Architecting the Human Intranet","authors":"J. Rabaey, A. Arias, Rikky Muller","doi":"10.1109/ESSCIRC53450.2021.9567774","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567774","url":null,"abstract":"Equipping us humans with the necessary tools to interact with, survive, and prosper in a rapidly changing world may require us to intimately adopt some of the same technologies that are causing some of these changes. Various wearable devices have been or are being developed to do just that. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. How to effectively do so in light of the many challenges from an efficiency, usability, and effectiveness perspective is the focus of this paper.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 239–298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications 一种基于先进130纳米SiGe BiCMOS技术的239-298 GHz功率放大器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567853
T. Bücher, J. Grzyb, P. Hillger, H. Rücker, B. Heinemann, U. Pfeiffer
{"title":"A 239–298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications","authors":"T. Bücher, J. Grzyb, P. Hillger, H. Rücker, B. Heinemann, U. Pfeiffer","doi":"10.1109/ESSCIRC53450.2021.9567853","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567853","url":null,"abstract":"A broadband 3-stage pseudo-differential SiGe power amplifier, fabricated in an experimental 130 nm SiGe BiC-MOS technology with ft/ f max of 470/650 GHz, is presented in this paper. Coupled-line matching networks with optimized impedance ratios are used to maximize bandwidth and output power while maintaing flat power gain and group delay for wireless communications applications. The amplifier provides a maximum small-signal power gain of 17.9 dB and a peak Psat/OP1dB of 6.7/5.2 dBm, respectively. A record small-signal and saturated power 3-dB bandwidth of 59 GHz (239–298 GHz) and 89 GHz (226–315 GHz), respectively is achieved. The DC power consumption is about 417 mW with a power-added-efficiency of 0.92% at 267 GHz. Without the included Balun which is needed for probing, the amplifier's Psatis increased to 8.1 dBm, while a maximum smallsignal gain of 20.2 dB is reached.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115566923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High-Conductance, Ohmic-like HfZrO4 Ferroelectric Memristor 高电导，类欧姆HfZrO4铁电记忆电阻
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567870
L. Bégon-Lours, M. Halter, Y. Popoff, Zhenming Yu, D. F. Falcone, B. Offrein
{"title":"High-Conductance, Ohmic-like HfZrO4 Ferroelectric Memristor","authors":"L. Bégon-Lours, M. Halter, Y. Popoff, Zhenming Yu, D. F. Falcone, B. Offrein","doi":"10.1109/ESSCIRC53450.2021.9567870","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567870","url":null,"abstract":"The persistent and switchable polarization of ferroelectric materials based on HfO2-bascd ferroelectric compounds, compatible with large-scale integration, are attractive synaptic elements for neuromorphic computing. To achieve a record current density of 0.01 A/cm2(at a read voltage of 80 mV) as well as ideal memristive behavior (linear current-voltage relation and analog resistive switching), devices based on an ultra-thin (2.7 nm thick), polycrystalline HfZrO4 ferroelectric layer are fabricated by Atomic Layer Deposition. The use of a semiconducting oxide interlayer (WOx<3) at one of the interfaces, induces an asymmetric energy profile upon ferroelectric polarization reversal and thus the long-term potentiation / depression (conductance increase / decrease) of interest. Moreover, it favors the stable retention of both the low and the high resistive states. Thanks to the low operating voltage (<3.5 V), programming requires less than 10−12 J for 20 ns long pulses. Remarkably, the memristors show no wake-up or fatigue effect.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127091054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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