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ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring 用于电化学监测的96通道40nm CMOS全集成电位器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567858
Peishuo Li, Tom R. Molderez, M. Verhelst
{"title":"A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring","authors":"Peishuo Li, Tom R. Molderez, M. Verhelst","doi":"10.1109/ESSCIRC53450.2021.9567858","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567858","url":null,"abstract":"Multi-channel potentiostats are required for monitoring electrochemical processes in a time- and cost- efficient manner. State-of-the-art PCB potentiostats suffer from a limited number of channels and limited bandwidth. Existing integrated CMOS potentiostats enable more parallel sensing channels, yet are still limited in the number of parallel stimulation channels and their bandwidth. The presented 40nm CMOS potentiostat chip overcomes this bottleneck with 96 individually controllable channels with 125dB current dynamic range and up to 150kHz bandwidth using an on-chip digital feedback controller. The chip supports both on-chip and off-chip electrodes allowing flexible electrode dimensions.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124291028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency 具有专用校准技术和确定性延迟的实时输出50-GS/s 8位TI-ADC
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567780
Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, L. Wu, Lei Zhou, Jin Wu, Xinyu Liu
{"title":"A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency","authors":"Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, L. Wu, Lei Zhou, Jin Wu, Xinyu Liu","doi":"10.1109/ESSCIRC53450.2021.9567780","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567780","url":null,"abstract":"This paper presents a real-time output 50-GS/s 8-bit time-interleaved analog-to-digital converter (ADC) with dedicated calibration techniques and deterministic latency, where the full-speed converted data are output by 16-lane transmitters. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse-fine two-step time-skew calibration are combined to optimize the ADC's performance. An edge detector and phase selector associated with a pair of common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 40-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.80 dB at 50 GS/s with a 19.123-GHz input, where 10.25 dB and 7.05 dB is optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.232 mm2 and consumes 894 mW.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET 7nm FinFET的112Gb/s PAM-4和168Gb/s PAM-8 7位dac发射机
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567801
Euhan Chong, F. A. Musa, Ahmed N. Mustafa, Tim Gao, Peter Krotnev, R. Soreefan, Qian Xin, P. Madeira, D. Tonietto
{"title":"A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET","authors":"Euhan Chong, F. A. Musa, Ahmed N. Mustafa, Tim Gao, Peter Krotnev, R. Soreefan, Qian Xin, P. Madeira, D. Tonietto","doi":"10.1109/ESSCIRC53450.2021.9567801","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567801","url":null,"abstract":"This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116245205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Ultra-Low Power K band Balanced Frequency Doubler with a Novel Current-reused Structure 一种新型电流复用结构的超低功耗K波段平衡倍频器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567776
Yue Gong, Jiangbo Chen, Likang Du, Huiyan Gao, Jiabing Liu, Shengjie Wang, Huan Li, Chunyi Song, Zhiwei Xu
{"title":"An Ultra-Low Power K band Balanced Frequency Doubler with a Novel Current-reused Structure","authors":"Yue Gong, Jiangbo Chen, Likang Du, Huiyan Gao, Jiabing Liu, Shengjie Wang, Huan Li, Chunyi Song, Zhiwei Xu","doi":"10.1109/ESSCIRC53450.2021.9567776","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567776","url":null,"abstract":"An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. The current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0 dBm, and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125967145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA 基于电感稳定OTA的17mw 33dbm IB-OIP3 0.5-1.5 GHz带宽TIA
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567850
Nimesh Nadishka Miral, D. Manstretta, R. Castello
{"title":"A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA","authors":"Nimesh Nadishka Miral, D. Manstretta, R. Castello","doi":"10.1109/ESSCIRC53450.2021.9567850","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567850","url":null,"abstract":"A highly linear Trans-Impedance Amplifier (TIA) for 5G New Radio mobile communication receivers is presented. The TIA has a cut-off frequency programmable from 500 MHz up to 1.5 GHz. The TIA is based on a Feed-Forward compensated amplifier. To ensure stability while achieving high bandwidth and low power, an inductor is used inside the feed-forward stage. A test chip has been realized in 28 nm CMOS technology. The TIA achieves an In-band OIP3 of 32.9 dBm and the output integrated noise from 20 MHz to 1.5 GHz is lower than 300 µ Vrms with a power dissipation of 17 mW.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC 基于二进制搜索ADC的零跳限可重构SRAM内存计算宏
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567819
Chengshuo Yu, K. Chai, T. T. Kim, Bongjin Kim
{"title":"A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC","authors":"Chengshuo Yu, K. Chai, T. T. Kim, Bongjin Kim","doi":"10.1109/ESSCIRC53450.2021.9567819","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567819","url":null,"abstract":"This work proposes a reconfigurable SRAM in-memory computing macro for processing neural networks using a pair of 7T bitcells. The proposed dual 7T bitcell structure decouples the read operation and offers a reconfigurable weight precision (3–15 levels). It also saves computing energy by skipping zeros for both weights and input activations. A 528×128 dual 7T bitcell array is constructed for the massively parallel 128 dot-products between reconfigurable precision weights (1.6-3.9bit) and binary inputs. A column consists of 384 bitcells for dot-products, 96 bitcells for ADC, and 48 bitcells for offset calibration. The bitcells for the column-by-column binary searching ADC are divided into two groups, each with 48 bitcells having fixed ‘+1’ or ‘-1’ weight. The column ADC then converts an analog dot-product result into a 5-7bit digital output code by dynamically changing the reference level through controlling the inputs for the 96 replica bitcells. A test-chip is fabricated using 65nm and the proposed bitcell array occupies 0.378mm2. The energy efficiency of a unit multiply-and-accumulate (MAC) operation is 258.5/67.9/23.9TOPS/W at 1.6/2.8/3.9bit weight using 0.45/0.8V supply voltages and 200MHz operating clock frequency.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129454873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An Optimized Low-Power Band-Tuning TX for Short-Range FMCW Radar in 22-nm FDSOI CMOS 基于22nm FDSOI CMOS的近程FMCW雷达低功耗带调谐TX优化
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567815
Sammy Cerida Rengifo, F. Chicco, E. Roux, C. Enz
{"title":"An Optimized Low-Power Band-Tuning TX for Short-Range FMCW Radar in 22-nm FDSOI CMOS","authors":"Sammy Cerida Rengifo, F. Chicco, E. Roux, C. Enz","doi":"10.1109/ESSCIRC53450.2021.9567815","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567815","url":null,"abstract":"The paper presents a low-power transmitter (TX) as a part of a fully integrated 57-66 GHz FMCW radar system. The TX path includes a BPSK modulator and it is optimized for short-range operation with 0 dBm output power. A band-tuning technique is used for covering the 9 GHz band and it is tuned as the LO frequency is swept. The LO distribution is designed in a modular approach to be able to extend the number of TX paths for MIMO operation. Integrated in GF 22-nm FDSOI CMOS technology, each TX path is 570x100 µm2 and consumes 17mW.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"145 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An a-IGZO TFT based Op-Amp with 57 dB DC-Gain, 311 KHz Unity-gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate 基于a-IGZO TFT的运算放大器，具有57 dB直流增益，311 KHz单位增益频率，75°相位裕度和2.43 mW柔性衬底功率
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567794
Mohit Dandekar, K. Myny, W. Dehaene
{"title":"An a-IGZO TFT based Op-Amp with 57 dB DC-Gain, 311 KHz Unity-gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate","authors":"Mohit Dandekar, K. Myny, W. Dehaene","doi":"10.1109/ESSCIRC53450.2021.9567794","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567794","url":null,"abstract":"This paper presents an internally compensated two stage operational amplifier fabricated using unipolar a-IGZO TFT devices integrated on flexible polyimide substrate. A new active load configuration is introduced to realize high incremental impedance and serve as the stage load of the amplifier. The opamp has been manufactured and measured to have 57 dB of open-loop DC-gain and a unity gain frequency of 311 kHz. Further, the internal compensation sets the dominant pole of the opamp achieving a phase margin of 75 degrees. A common mode feedback scheme has been implemented to bias the fully differential gain stages using an auxiliary two-stage OpAmp realized with a conventional diode-connected transistor stage load. This design, to our knowledge, surpasses the highest reported performance of (operational) amplifiers made in a-IGZO technology.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS 在22nm FD-SOI CMOS中使用后门偏置的具有精细相位调谐能力的28 ghz开关滤波器移相器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567845
E. Kobal, T. Siriburanon, R. Staszewski, A. Zhu
{"title":"A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS","authors":"E. Kobal, T. Siriburanon, R. Staszewski, A. Zhu","doi":"10.1109/ESSCIRC53450.2021.9567845","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567845","url":null,"abstract":"This paper introduces a phase shifter based on switched filters for mm-wave 5G MIMO transmitters. It is realized in 22 nm FD-SOI CMOS and exploits the use of back-gate biasing. The new approach features strong tolerance to process, voltage and temperature (PVT) variations and thus can maintain low phase error with fine phase tuning capability supporting a large bandwidth. Measurement results show that the 4-bit phase shifter achieves 3.5° rms phase error at 28 GHz. The proposed phase shifter can maintain <5° of the worst-case rms phase error when operating across 24 to 29.5 GHz resulting in 20.56% fractional bandwidth which is the largest among the published switched-filter phase shifters to date.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter 双模二阶过采样模数转换器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567825
Abhijeet D. Taralkar, F. Conzatti, P. Malcovati, A. Baschirotto
{"title":"A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter","authors":"Abhijeet D. Taralkar, F. Conzatti, P. Malcovati, A. Baschirotto","doi":"10.1109/ESSCIRC53450.2021.9567825","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567825","url":null,"abstract":"This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4 µm devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129996572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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