A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency

This paper presents a real-time output 50-GS/s 8-bit time-interleaved analog-to-digital converter (ADC) with dedicated calibration techniques and deterministic latency, where the full-speed converted data are output by 16-lane transmitters. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse-fine two-step time-skew calibration are combined to optimize the ADC's performance. An edge detector and phase selector associated with a pair of common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 40-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.80 dB at 50 GS/s with a 19.123-GHz input, where 10.25 dB and 7.05 dB is optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.232 mm2 and consumes 894 mW.