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ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)最新文献

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An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping 带有占空比放大器和数字预测失配误差整形的80dB-SNDR 98dB-SFDR噪声整形SAR ADC
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567748
Hanyue Li, Yuting Shen, Haoming Xin, E. Cantatore, P. Harpe
{"title":"An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping","authors":"Hanyue Li, Yuting Shen, Haoming Xin, E. Cantatore, P. Harpe","doi":"10.1109/ESSCIRC53450.2021.9567748","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567748","url":null,"abstract":"This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130217966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FDDAC-based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate 基于fddac的2 GHz调制带宽和8 Gbit/s数据速率发射机
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567775
Oner Hanay, Erkan Bayram, A. Hamed, R. Negra
{"title":"FDDAC-based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate","authors":"Oner Hanay, Erkan Bayram, A. Hamed, R. Negra","doi":"10.1109/ESSCIRC53450.2021.9567775","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567775","url":null,"abstract":"This paper presents a transmitter (Tx) concept which generates a wide coherent modulation bandwidth (BW) while attenuating the out-of-band emissions without oversampling and digital filtering. The proposed Fourier-Domain digital-to-analogue converter (FDDAC) based Tx concept exploits the relation between the discrete- and continuous-time Fourier Transform leading to intrinsic Nyquist filtering. Thus, the sample rates in the analogue-mixed-signal and the entire digital signal processor (DSP) blocks are reduced by up to two orders of magnitude compared to conventional Txs. The experimentally verified Tx-IC for 802.11ad/y applications generates a single-carrier signal with a modulation BW of up to 2 GHz and 16QAM. The occupied chip area is 3.6 mm2 including the DSP. The measured EVM values are 7.2% and 11.8% for a 1 and 2 GHz QPSK signal, whereas they are 9.6% and 13.9% for a 1 and 2 GHz-wide 16QAM signal, respectively. Thus, the maximum demonstrated data rate is 8 Gbit/s.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks 考虑内间隔层和外延诱发应力的GAA纳米片场效应管的性能权衡方案:理解和减轻工艺风险
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567879
Amita Rawat, K. Bhuwalka, P. Matagne, B. Vermeersch, Hao Wu, G. Hellings, J. Ryckaert, Changze Liu
{"title":"Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks","authors":"Amita Rawat, K. Bhuwalka, P. Matagne, B. Vermeersch, Hao Wu, G. Hellings, J. Ryckaert, Changze Liu","doi":"10.1109/ESSCIRC53450.2021.9567879","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567879","url":null,"abstract":"This paper benchmark the intrinsic trade-off between two essential modules of gate-all-around GAA nanosheet (NS)FETs viz. inner-spacers (ISPs) epi-induced stress in the channel. While having both ISPs and the stress is the best-case scenario for NSFET, it comes with enhanced process challenges and performance risks: poor epi-quality resulting in a no-channel stress scenario. While inner-spacers are important to parasitic capacitance reduction, we show that having intrinsic epi-stress is more beneficial and provides a better performance trade-off. We further evaluate the impact of inner-spacer κ-value and enhanced epi-volume for the two different cases. Finally, we have performed self-heating studies to show how skipping inner-spacers can provide additional reduction in peak temperature.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode 1.15 TOPS/W, 16核并行超低功耗集群，具有2b至32b完全灵活的位精度和矢量锁步执行模式
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567767
Angelo Garofalo, G. Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, L. Benini, D. Rossi
{"title":"A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode","authors":"Angelo Garofalo, G. Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, L. Benini, D. Rossi","doi":"10.1109/ESSCIRC53450.2021.9567767","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567767","url":null,"abstract":"IoT end-nodes require extreme performance and energy efficiency coupled with high flexibility to deal with the increasing computational requirements and variety of modern near-sensor data analytics applications. Low-Bitwidth and Mixed-Precision arithmetic is emerging as a trend to address the near-sensor analytics challenge in several fields such as linear algebra, Deep Neural Networks (DNN) inference, and on-line learning. We present Dustin, a fully programmable Multiple Instruction Multiple Data (MIMD) cluster integrating 16 RISC-V cores featuring 2b-to-32b bit-precision instruction set architecture (ISA) extensions enabling fine-grain tunable mixed-precision computation, improving performance and efficiency by 3.7 x and 1.9 x over state-of-the-art fully programmable devices. The cluster can be dynamically configured in Vector Lockstep Execution Mode (VLEM), turning off all IF stages except one, reducing power consumption by up to 38% with no performance degradation. The cluster, implemented in 65nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126231112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI 采用28nm FD-SOI的带Wordline Boost的低电压6T双端口SRAM
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567785
Masoud Nouripayam, J. Rodrigues, Xiao Luo, Tom Johansson, B. Mohammadi
{"title":"A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI","authors":"Masoud Nouripayam, J. Rodrigues, Xiao Luo, Tom Johansson, B. Mohammadi","doi":"10.1109/ESSCIRC53450.2021.9567785","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567785","url":null,"abstract":"A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121582209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advancements in indirect Time of Flight image sensors in front side illuminated CMOS 正面照明CMOS中间接飞行时间图像传感器的研究进展
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567750
M. Dielacher, Martin Flatscher, R. Gabl, R. Gaggl, D. Offenberg, J. Prima
{"title":"Advancements in indirect Time of Flight image sensors in front side illuminated CMOS","authors":"M. Dielacher, Martin Flatscher, R. Gabl, R. Gaggl, D. Offenberg, J. Prima","doi":"10.1109/ESSCIRC53450.2021.9567750","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567750","url":null,"abstract":"We will present major advances in Time of Flight (ToF) image sensors for consumer applications. Several innovative elements integrated into a 130nm front side illumination CMOS node reveal superior sensor performance so far only attributed to much more complex backside illumination technologies. The gate controlled pixels comprising deep trenches, buried mirrors and integrated prisms, reveal high quantum efficiency and modulation transfer function (MTF) close to the physical pixel size. In-pixel common mode suppression prevents saturation even under backlight conditions. The comprehensive System on Chip integrates high speed ADCs, a flexible phase shifter, as well as current monitoring for laser safety.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Broadband 110–170 GHz Frequency Multiplier by 4 Chain with 8 dBm Output Power in 130 nm BiCMOS 130 nm BiCMOS中输出功率为8 dBm的宽带4链110-170 GHz倍频器
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567797
A. Karakuzulu, M. Eissa, D. Kissinger, A. Malignaggi
{"title":"A Broadband 110–170 GHz Frequency Multiplier by 4 Chain with 8 dBm Output Power in 130 nm BiCMOS","authors":"A. Karakuzulu, M. Eissa, D. Kissinger, A. Malignaggi","doi":"10.1109/ESSCIRC53450.2021.9567797","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567797","url":null,"abstract":"This work presents a broadband and high power D-band multiplier by 4 chain designed in a 130 nm silicon-germanium (SiGe) BiCMOS technology. A single-ended 35 GHz input signal is made differential by a Marchand balun and multiplied by 4 by means of a Gilbert cell based quadrupler. The undesired harmonics are filtered out by a double section harmonic filter and, after a D-Band Marchand balun employed for differential to single conversion, amplified using a broadband 3-stage cascode amplifier. The presented circuit achieves a 3-dB bandwidth of 60 GHz, covering the entire D-band (110 GHz to 170 GHz) with a peak saturated output power of 8 dBm. A rejection of more than 40 dB has been measured for 3rd, 5th, 6th and 7th harmonics at 140 GHz. The designed circuit consumes 280 mW from a 3.3 V supply, resulting in a drain efficiency of 1.75%. The proposed solution shows a 43 % relative bandwidth, which is, to the best of the authors' knowledge, the largest among the up to now published silicon based D-band frequency multiplier by 4 chains.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114068527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback 采用频率转换反馈的4-31GHz直接转换接收机
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567779
J. Dean, S. Hari, Avinash Bhat, B. Floyd
{"title":"A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback","authors":"J. Dean, S. Hari, Avinash Bhat, B. Floyd","doi":"10.1109/ESSCIRC53450.2021.9567779","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567779","url":null,"abstract":"This paper presents a multi-band direct-conversion receiver with frequency-translated feedback. The forward path includes a low-noise transconductance amplifier followed by four-phase passive mixers which drive baseband amplifiers, and the feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable frequency-selective input matching. The receiver operates from 4–31 GHz exhibiting greater than 25 dB gain through 22 GHz and greater than 17 dB gain through 31 GHz. Noise figure is 5.2 to 9.8 dB, rising with frequency; input-referred 1-dB compression point is -17 dBm; and in-band IIP3 is -6.6 dBm. Out-of-band 1-dB blocker compression is greater than -12 dBm. The receiver core consumes 91 mW, whereas an integrated 2:1 frequency divider and pass-gate buffer for generating non-overlapping four-phase clocks consumes an additional 87–227 mW from 4–31 GHz, respectively.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131140072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Emulating artificial mechanoreceptor functionalities from SiO2-based memristor and PDMS stretchable sensor for artificial skin applications 模拟人造皮肤应用的基于sio2的忆阻器和PDMS可拉伸传感器的人工机械感受器功能
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567875
P. Bousoulas, Charalampos Papakonstantinopoulos, D. Tsoukalas
{"title":"Emulating artificial mechanoreceptor functionalities from SiO2-based memristor and PDMS stretchable sensor for artificial skin applications","authors":"P. Bousoulas, Charalampos Papakonstantinopoulos, D. Tsoukalas","doi":"10.1109/ESSCIRC53450.2021.9567875","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567875","url":null,"abstract":"The development of robust artificial sensory systems that will be able to detect, memorize and respond to external stimuli is attracting a considerable amount of interest over the last years towards emulating artificial skin properties. Skin is the largest sensory system of the human body that carries out complex procedures by employing a variety of biological receptors. However, it is quite difficult to acquire stretchable artificial skin functionalities by combining the present tactile sensors. Along these lines, we report here a sensory system that has the ability to detect various strain loads with excellent sensitivity and at the same time respond and store the applied stimuli. In order to attain this goal, we used a bipolar switching memory device made on poly-ethylene naphthalate (PEN) substrate and Pt nanoparticles (NPs)-based sensor on poly-dimethylsiloxane (PDMS). The memristor operates only under strain conditions and retains the induced resistance changes even when the applied stain gauge is removed with <20% resistance attenuation. The sensing element exhibits a colossal gauge factor (GF) of 109, which is utilized in order to produce sharp and distinct responses. Moreover, the memristive element exhibits also a quite large memory window (~105) which can be leveraged in order to assimilate various external stimuli. Additionally, paired-pulse facilitation (PPF) and long-term plasticity (LTP) effects are demonstrated indicating the potential perspective of our approach to performing neuromorphic computations with low power consumption.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128122764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing 用于量子计算的16nm FinFET技术的低温表征
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2021-09-13 DOI: 10.1109/ESSCIRC53450.2021.9567747
Hung-Chi Han, F. Jazaeri, Antonio A. D'Amico, A. Baschirotto, E. Charbon, C. Enz
{"title":"Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing","authors":"Hung-Chi Han, F. Jazaeri, Antonio A. D'Amico, A. Baschirotto, E. Charbon, C. Enz","doi":"10.1109/ESSCIRC53450.2021.9567747","DOIUrl":"https://doi.org/10.1109/ESSCIRC53450.2021.9567747","url":null,"abstract":"This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16 nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95 K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116266890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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