{"title":"一种新型电流复用结构的超低功耗K波段平衡倍频器","authors":"Yue Gong, Jiangbo Chen, Likang Du, Huiyan Gao, Jiabing Liu, Shengjie Wang, Huan Li, Chunyi Song, Zhiwei Xu","doi":"10.1109/ESSCIRC53450.2021.9567776","DOIUrl":null,"url":null,"abstract":"An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. The current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0 dBm, and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An Ultra-Low Power K band Balanced Frequency Doubler with a Novel Current-reused Structure\",\"authors\":\"Yue Gong, Jiangbo Chen, Likang Du, Huiyan Gao, Jiabing Liu, Shengjie Wang, Huan Li, Chunyi Song, Zhiwei Xu\",\"doi\":\"10.1109/ESSCIRC53450.2021.9567776\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. The current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0 dBm, and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.\",\"PeriodicalId\":129785,\"journal\":{\"name\":\"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC53450.2021.9567776\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC53450.2021.9567776","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Ultra-Low Power K band Balanced Frequency Doubler with a Novel Current-reused Structure
An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. The current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0 dBm, and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.
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