{"title":"用于22nm FDSOI低功耗FMCW雷达的60ghz QDCO和11ghz无缝调谐","authors":"F. Chicco, Sammy Cerida Rengifo, E. Roux, C. Enz","doi":"10.1109/ESSCIRC53450.2021.9567787","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a 60 GHz Quadrature Digitally-Controlled Oscillator for a low-power Frequency-Modulated Continuous Wave radar System-on-Chip. The accurate detection of vital signs requires I and Q demodulation of the received signal. The quadrature coupling is exploited to achieve a seamless and ultra wide frequency tuning range of 11GHz. The oscillator is designed for integration in an All-Digital Phase-Locked Loop. The presented technique allows to simplify the interface with the digital loop filter without the need for an extensive calibration. A wide-band and low-power divider chain is designed as well using dynamic topologies. The circuits are integrated in GF 22-nm FDX CMOS technology and consume between 12.8 and 22.4 mW across the frequency range (17.6mW on average) with a supply voltage of 0.8V.","PeriodicalId":129785,"journal":{"name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 60 GHz QDCO with 11 GHz Seamless Tuning for Low-Power FMCW Radars in 22-nm FDSOI\",\"authors\":\"F. Chicco, Sammy Cerida Rengifo, E. Roux, C. Enz\",\"doi\":\"10.1109/ESSCIRC53450.2021.9567787\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a 60 GHz Quadrature Digitally-Controlled Oscillator for a low-power Frequency-Modulated Continuous Wave radar System-on-Chip. The accurate detection of vital signs requires I and Q demodulation of the received signal. The quadrature coupling is exploited to achieve a seamless and ultra wide frequency tuning range of 11GHz. The oscillator is designed for integration in an All-Digital Phase-Locked Loop. The presented technique allows to simplify the interface with the digital loop filter without the need for an extensive calibration. A wide-band and low-power divider chain is designed as well using dynamic topologies. The circuits are integrated in GF 22-nm FDX CMOS technology and consume between 12.8 and 22.4 mW across the frequency range (17.6mW on average) with a supply voltage of 0.8V.\",\"PeriodicalId\":129785,\"journal\":{\"name\":\"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC53450.2021.9567787\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC53450.2021.9567787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 60 GHz QDCO with 11 GHz Seamless Tuning for Low-Power FMCW Radars in 22-nm FDSOI
This paper presents the design of a 60 GHz Quadrature Digitally-Controlled Oscillator for a low-power Frequency-Modulated Continuous Wave radar System-on-Chip. The accurate detection of vital signs requires I and Q demodulation of the received signal. The quadrature coupling is exploited to achieve a seamless and ultra wide frequency tuning range of 11GHz. The oscillator is designed for integration in an All-Digital Phase-Locked Loop. The presented technique allows to simplify the interface with the digital loop filter without the need for an extensive calibration. A wide-band and low-power divider chain is designed as well using dynamic topologies. The circuits are integrated in GF 22-nm FDX CMOS technology and consume between 12.8 and 22.4 mW across the frequency range (17.6mW on average) with a supply voltage of 0.8V.