200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator

Abstract

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25% duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.