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Investigation of defect microstructures responsible for NBTI degradation using effective dipole moment extraction 利用有效偶极矩提取研究NBTI降解的缺陷微观结构
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038620
H. Tahi, B. Djezzar, Karim Benmassai, M. Boubaaya, A. Benabdelmoumene, A. Chenouf, M. Goudjil
{"title":"Investigation of defect microstructures responsible for NBTI degradation using effective dipole moment extraction","authors":"H. Tahi, B. Djezzar, Karim Benmassai, M. Boubaaya, A. Benabdelmoumene, A. Chenouf, M. Goudjil","doi":"10.1109/IDT.2014.7038620","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038620","url":null,"abstract":"The identification of the microstructure defects responsible of metal-oxide-silicon field effect transistor (MOSFET) reliability problems is important to understand, the physical mechanisms behind these problems. In this paper, the effective dipole moment of bond precursors that contribute to negative bias temperature instability (NBTI) permanent components is investigated, using the conventional charge pumping method (CCP). In addition, the contribution of the several precursors to the extracted effective dipole moment is modelled. The model is in agreement with the experimental data. The results show that the effective dipole moments responsible of NBTI permanent component correspond to Si-H and stretched Si-O bonds. The Si-H bond dipole moment clearly dominates at low stress electric field (Eox) and when their density is higher than that Si-O bond. While, the effective dipole moment of Si-O bonds is obviously observable at high stress electric field even with low density. However, for intermediate stress electric field, both effective dipole moments contribute and lead an inaccurate extraction. Moreover, the profiling of the effective dipole moment along the transistor channel, shows that Si-H and stretched Si-O bonds are mostly located in the vicinity of the LDD region.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129229405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical approach of the impact of through silicon via on the performance of MOS devices 通硅通孔对MOS器件性能影响的分析方法
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038621
Benkechkache Mohamed El Amine, S. Latreche, G. Betta
{"title":"Analytical approach of the impact of through silicon via on the performance of MOS devices","authors":"Benkechkache Mohamed El Amine, S. Latreche, G. Betta","doi":"10.1109/IDT.2014.7038621","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038621","url":null,"abstract":"Current innovations in electronics combine performance, size and cost criteria. Nevertheless, in the all-digital era, the 2D technology and the fabrication of CMOS Integrated Circuit are approaching their ultimate limits. As a result, the use of 3D technology in the fabrication of different Integrated Circuits becomes very appealing. Among the aspects of the 3D Integration we find the Through Silicon Vias (TSVs), short vertical interconnects that convey the different layers all kind of signals. 3D integration, first introduced for memory chips, has later found increasing application to other domains in microelectronics. The aim of this research is to investigate the electrical performances of MOS devices which have nearby such a type of interconnects (TSVs) in view of optimizing their behavior with the implementation of an analytical model able to describe the TSVs behavior at the circuit level in order to predict and optimize the performance of MOS devices with 3D-TSV interconnect. The accuracy of this model is eventually validated using numerical TCAD simulations.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124643884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck 使用忆阻交叉网络的并行计算:消除处理器-内存瓶颈
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038603
Alvaro Velasquez, Sumit Kumar Jha
{"title":"Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck","authors":"Alvaro Velasquez, Sumit Kumar Jha","doi":"10.1109/IDT.2014.7038603","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038603","url":null,"abstract":"We are quickly reaching an impasse to the number of transistors that can be squeezed onto a single chip. This has led to a scramble for new nanotechnologies and the subsequent emergence of new computing architectures capable of exploiting these nano-devices. The memristor is a promising More-than-Moore device because of its unique ability to store and manipulate data on the same device. In this paper, we propose a flexible architecture of memristive crossbar networks for computing Boolean formulas. Our design nullifies the gap between processor and memory in von Neumann architectures by using the crossbar both for the storage of data and for performing Boolean computations. We demonstrate the effectiveness of our approach on practically important computations, including parallel Boolean matrix multiplication.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120856157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.9 V low power reconfigurable CMOS folded cascode LNA for multi-standard wireless applications 用于多标准无线应用的0.9 V低功耗可重构CMOS折叠级联电路
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038610
A. Taibi, A. Slimane, Sid-Ahmed Tedjini-Bailiche, M. Belaroussi, D. Maafri, M. Trabelsi
{"title":"A 0.9 V low power reconfigurable CMOS folded cascode LNA for multi-standard wireless applications","authors":"A. Taibi, A. Slimane, Sid-Ahmed Tedjini-Bailiche, M. Belaroussi, D. Maafri, M. Trabelsi","doi":"10.1109/IDT.2014.7038610","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038610","url":null,"abstract":"In This paper, a reconfigurable CMOS folded cascode LNA for multi-standard wireless applications is presented, including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated folded-cascode topology for low voltage applications, the proposed LNA achieves a good trade-off between good gain, noise figure and power consumption. The input and output matching networks include capacitor switches devices to control the band selection for multi-standard purpose. Implemented in 0.13-μm CMOS technology, the simulated results perform a maximum power gain of 20.82 dB, a noise figure below 1.72 dB, an input and output return loss less than -14 dB and -15 dB, respectively. The LNA achieves -15 dBm of a minimum third-order input intercept point at input frequency of 2.4 GHz. For all standards the proposed LNA consumes only 5.15 mW from 0.9 V supply voltage.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133642123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design, manufacturing & test of integrated circuits in the nanotechnology era 纳米技术时代集成电路的设计、制造和测试
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038579
O. Kebichi
{"title":"Design, manufacturing & test of integrated circuits in the nanotechnology era","authors":"O. Kebichi","doi":"10.1109/IDT.2014.7038579","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038579","url":null,"abstract":"This article is meant to highlight the state of the art of chip design, manufacturing and test and the challenges it is facing while keeping up with Moore's law at the nanoscale technology node. We will outline the different challenges the semiconductor industry is facing at sub-45 nm and highlight the different approaches the engineering community is adopting in the design, manufacturing and test fields.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"35 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114386100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A survey of GF (2m) multipliers on FPGA FPGA上GF (2m)乘法器的研究
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038616
Haichour Amina Selma, M. Hamadouche
{"title":"A survey of GF (2m) multipliers on FPGA","authors":"Haichour Amina Selma, M. Hamadouche","doi":"10.1109/IDT.2014.7038616","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038616","url":null,"abstract":"Finite field multiplication is one of the most important operation in the finite field arithmetic. This paper presents a study that compares the architectures and the performances of some of the major GF (2m) multiplication algorithms. Hardware implementation on a reconfigurable circuit (FPGA) allowed assessment of the performance of architecture multipliers in terms of area and time complexities. Results show that serial/sequential multipliers require less area and lead to a small computational drawback, whereas parallel/combinational multipliers consume more area but are faster. Thus a trade-off between area and speed should be obtained using hybrid multipliers.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An independent dual gate SOI FinFET soft-error resilient memory cell 一种独立的双栅极SOI FinFET软误差弹性存储单元
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038584
Nikolaos Eftaxiopoulos-Sarris, N. Axelos, Georgios Zervakis, Kostas Tsoumanis, K. Pekmestzi
{"title":"An independent dual gate SOI FinFET soft-error resilient memory cell","authors":"Nikolaos Eftaxiopoulos-Sarris, N. Axelos, Georgios Zervakis, Kostas Tsoumanis, K. Pekmestzi","doi":"10.1109/IDT.2014.7038584","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038584","url":null,"abstract":"In this paper we present an 8T footless storage element, the FFDICE (FinFET DICE), a dual interlocked structure using Independent Gate SOI FinFET transistors that exhibits soft error resilience characteristics. Compared to the conventional DICE cell, the proposed design achieves area savings by dispensing with the four NMOS driver transistors, retains the excellent tolerance characteristics to single node upsets and similar multiple node upset resilience. Of significance to modern designs that apply voltage scaling techniques to achieve power savings, simulation results on Static Voltage Noise Margin and Static Current Noise Margin metrics show that the proposed cell exhibits excellent stability across an examined voltage range of 0.75V to 1V.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123148598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of silicon MEMS capacitive pressure sensor for biomédical applications 生物医学用硅MEMS电容式压力传感器的建模
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038625
Lakhdari Abdelghani, MekkakiaMaaza Nasr-Eddine, Maamar Azouza, Bouguenna Abdellah, Kichene Moadh
{"title":"Modeling of silicon MEMS capacitive pressure sensor for biomédical applications","authors":"Lakhdari Abdelghani, MekkakiaMaaza Nasr-Eddine, Maamar Azouza, Bouguenna Abdellah, Kichene Moadh","doi":"10.1109/IDT.2014.7038625","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038625","url":null,"abstract":"This paper presents the Modeling of Silicon capacitive pressure sensor for biomédical applications. Using the Micro Electro Mechanical Systems (MEMS) technology, MEMS sensors are widely used in biomédical applications due to its advantages of miniaturization, low power consumption, easy to measurement and telemetry. This work demonstrates the design of MEMS based capacitive pressure sensor using finite element method (FEM). We will study the deflection of a fine membrane of silicon (100) of circular form to the perfectly embedded at its edges, under uniform and constant pressure. The capacitive response of the sensor obtained is linear in the range of pressure of 0-40KPa (0-300mmHg) with better sensitivity.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multi-device layout templates for nanometer analog design 纳米模拟设计的多器件布局模板
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038592
Mohannad Elshawy, M. Dessouky, S. Saif, Sherif Mansour, Eduard Petrus
{"title":"Multi-device layout templates for nanometer analog design","authors":"Mohannad Elshawy, M. Dessouky, S. Saif, Sherif Mansour, Eduard Petrus","doi":"10.1109/IDT.2014.7038592","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038592","url":null,"abstract":"With the advance of nanoscale fabrication processes, well-known common-centroid analog layout techniques are no longer sufficient to guarantee the required level of device matching. This paper proposes a complex multi-device layout generator of highly matched devices for analog circuit design. The proposed tool offers different placement techniques for alternative layouts, as well as different matching strategies with focus on common-centroid, lithography and stress effect mitigation. Device arrays are key for producing uniform, litho-friendly layouts. Generic array templates can be generated for transistors, resistors and capacitors. The layout of a switched-capacitor integrator is given as an example.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
WaferCatalyst — Towards promotion of IC design in the middle east using virtual community approach WaferCatalyst -使用虚拟社区方法促进中东IC设计
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038593
Shahab A. Najmi, A. Obeid, M. BenSaleh
{"title":"WaferCatalyst — Towards promotion of IC design in the middle east using virtual community approach","authors":"Shahab A. Najmi, A. Obeid, M. BenSaleh","doi":"10.1109/IDT.2014.7038593","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038593","url":null,"abstract":"WaferCatalyst is an initiative of King Abdulaziz City for Science and Technology (KACST) aimed at promoting integrated circuit (IC) design and related technologies in Saudi Arabia and the surrounding regions. KACST has undertaken a virtual community building approach utilizing conventional methods along with a fully custom web based portal for the complete automation of services and as a tool for community capacity building. The portal supports features like E-Learning, support services, video conferencing, order management and secure file transfer. These features are used to achieve high efficiency in providing services, creating an online community and to provide a mechanism for knowledge transfer and sharing. The results of this technology based approach in the second year are already very encouraging with participation from more than fourteen universities and organizations from four countries and a large number of users have signed up and are utilizing the system, thus contributing to the development of the ecosystem.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122079184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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