2014 9th International Design and Test Symposium (IDT)最新文献

Efficient embedded SoC hardware/software codesign using virtual platform 利用虚拟平台高效嵌入式SoC硬件/软件协同设计

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038583

M. El-Moursy, Ayman Sheirah, M. Safar, A. Salem

{"title":"Efficient embedded SoC hardware/software codesign using virtual platform","authors":"M. El-Moursy, Ayman Sheirah, M. Safar, A. Salem","doi":"10.1109/IDT.2014.7038583","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038583","url":null,"abstract":"A complete framework and methodology to design, simulate, and debug large SoC is presented. Full VP creation using efficient tools is described. An efficient tool to allow co-debug of HW/SW on VP is also presented. The tools enable debugging and analyzing an application and a Linux driver that run on the VP. Breakpoints and mon commands can be used to detect and correct errors, access registers and review their values. The tools provide simulation of SW and HW on the same timeline. They also, involve building, uploading and debugging a Linux driver on the VP. The procedure steps for debugging the application code on the VP are provided. How to create an analyzer project with an analyzer session to perform SW and HW analysis, and save the results are also described. Functions and capabilities to investigate the tracing results are presented. Preparing the Environment of Linux Software Development with VP is needed before running the debug flow. How to prepare the system environment is summarized. Complex applications can run on the VP. Debugging both the application and the Linux drivers, and analyzing both the SW and the HW are made easy. Powerful SW tracing is provided. HW architecture analysis is an additional domain to be explored by the methodology. SW and HW profiling is shown to be not only feasible, but also handy. Very graphical waveforms and user friendly environment with easy Graphical User Interface (GUI) show how flexible and powerful the methodology is. A test case demonstrating the flexibility and efficiency of our technique is presented.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126124168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Enhanced bit-width optimization for linear circuits with feedbacks 带反馈的线性电路的增强位宽优化

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038607

El-sedik Lamini, Rima Bellal, S. Tagzout, H. Belbachir, Adel Belouchrani

引用次数: 6

Nonvolatile memories: Present and future challenges 非易失性记忆:现在和未来的挑战

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038588

E. Vatajelu, H. Aziza, C. Zambelli

引用次数: 32

SAT-based speedpath debugging using X traces 使用X跟踪的基于sat的高速路径调试

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038595

M. Dehbashi, G. Fey

引用次数: 1

Scalable high speed serial interface for data converters: Using the JESD204B industry standard 用于数据转换器的可扩展高速串行接口:使用JESD204B工业标准

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038577

H. Saheb, Syed Haider

引用次数: 15

Modulo 2n+1 addition and multiplication for redundant operands 模2n+1的加法和乘法冗余操作数

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038614

Kostas Tsoumanis, C. Efstathiou, K. Pekmestzi

引用次数: 2

A comparative study of various microstrip bandpass filters topologies for UWB applications 超宽带应用中各种微带带通滤波器拓扑结构的比较研究

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038611

A. Saadi, M. Yagoub, R. Touhami

引用次数: 4

Reliability assessment of backward error recovery for SRAM-based FPGAs 基于sram的fpga后向错误恢复可靠性评估

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038622

F. Sahraoui, Ghaffari Fakhreddine, M. A. Benkhelifa, B. Granado

引用次数: 3

Day 2: Invited talk spintronic microsystems: Integrating analog devices with CMOS 第二天:邀请演讲自旋电子微系统:集成模拟器件与CMOS

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038573

P. Freitas

{"title":"Day 2: Invited talk spintronic microsystems: Integrating analog devices with CMOS","authors":"P. Freitas","doi":"10.1109/IDT.2014.7038573","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038573","url":null,"abstract":"One of the best know examples of integration of spintronic devices with CMOS is given by MRAM (magnetic random access memory), a digital memory where each node in its simplest form includes a switching element (transistor) in series with a magnetic tunnel junction (magnetic storage element). In the analog field, work is beginning in the design, fabrication, and back end integration of ASICS with magnetic sensors. This talk describes circuit design, integration process, fabrication and test of two different types of microsystems: a multiplexed protein/DNA biochip where an array of linear sensors (up to 256) fabricated on top of a 0.35um CMOS circuit detect in real time protein/DNA hibridization to immobilized probes. System noise (ASIC, sensor, fluidic environment) defines analyte minimum detectivity. A second example covers the design and fabrication of a non destructive testing platform, from the ASIC controlling sensor array readout, to the sensor array itself, consisting on an array of spin valve or magnetic tunnel junction elements. Depending on defect nature (buried or surface), signals need to be detected either at few hundred Hz, or at MHz level. System noise (ASIC and sensor noise) defines (for perfectly homogeneous samples) defect detection capability.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and implementation of Wishbone bridge for an iSLIP based NoC 基于iSLIP的NoC叉骨桥的设计与实现

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038615

Nejib Mediouni, Samir Ben Abid, O. Kallel, Kaouthar Guesmi, S. Hasnaoui

引用次数: 0