Design and implementation of Wishbone bridge for an iSLIP based NoC

Abstract

Multi-core processors and System On Chips (SoC) are becoming more and more ubiquitous in hand-held devices and super computers alike. The rise of those systems and the ever increasing integration rate have given rise to integrated networks to accommodate the bandwidth needs for highly parallel applications. In this paper, we present a Network On Chip (NoC) implementation with a Wishbone interface that would facilitate the transition from Wishbone-based SoCs to NoCs without major modifications. The proposed architecture is designed to be lightweight and have a low footprint while being fully transparent to the wishbone enabled wishbone-enabled IP cores.