2014 9th International Design and Test Symposium (IDT)最新文献_第5页

Day 2: Mini-tutorial: Challenges to the design and optimization of cyber-physical systems 第2天:迷你教程:网络物理系统设计和优化的挑战

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038574

Zebo Peng

{"title":"Day 2: Mini-tutorial: Challenges to the design and optimization of cyber-physical systems","authors":"Zebo Peng","doi":"10.1109/IDT.2014.7038574","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038574","url":null,"abstract":"Summary form only given. We are witnessing an exponential increase of cyber-physical systems where the computational components interact with the physical world in a tightly manner. More and more of these systems are nowadays used for safety-critical applications, such as automotive electronics and medical equipment. These safety-critical applications impose stringent requirements on reliability, efficiency, low-power and testability of the underlying VLSI hardware implementation. With silicon technology scaling, however, VLSI circuits is built with smaller transistors, perform at higher clock frequencies, run at lower voltage levels, and operate very often at higher temperature. All these have major negative impact on reliability, performance, power-efficiency and testability. We are therefore facing the challenges of how to address all these technical problems and their interplay with the stringent real-time requirements imposed by many safety-critical applications. This talk will discuss the design of such cyber-physical systems by considering both fault-tolerance and real-time requirements at the same time. It will describe several key challenges and some emerging solutions to the design and optimization of such systems. In particular, it will present time-redundancy based fault-tolerance techniques to address transient faults which have become more and more common in nano-scale technology. It will also describe several design tradeoffs including hardware/software co-design solutions for the optimization of cyber-physical systems.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A UVM-based smart functional verification platform: Concepts, pros, cons, and opportunities 基于uvm的智能功能验证平台:概念、优点、缺点和机会

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038594

K. Salah

引用次数: 41

Failure and root cause analysis for a system-on-chip: An industrial case study 片上系统的故障和根本原因分析:一个工业案例研究

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038578

S. Boubezari, Jayant Chhabria

引用次数: 0

Impact analysis of resistive bridge within deep submicron Secured CMOS circuits 深亚微米固定CMOS电路中电阻桥的冲击分析

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038597

G. A. Abdelmalek, R. Ziani

引用次数: 3

Rapid prototyping of PVS into FPGA: From model based design to FPGA/ASICs implementation PVS在FPGA中的快速原型设计:从基于模型的设计到FPGA/ asic的实现

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038606

S. Titri, C. Larbes, K. Youcef-Toumi

{"title":"Rapid prototyping of PVS into FPGA: From model based design to FPGA/ASICs implementation","authors":"S. Titri, C. Larbes, K. Youcef-Toumi","doi":"10.1109/IDT.2014.7038606","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038606","url":null,"abstract":"A wide variety of maximum power point tracking (MPPT) algorithms for photovoltaic systems (PVS) have been proposed and developed. These MPPT algorithms vary in many aspects such as the selected criteria and techniques used. In this paper, we propose an effective design methodology for hardware implementation of PVS into FPGA/ASICs. To achieve our goal, we propose the application of the model based design at high level using the Matlab/Simulink which includes the HDL Coder Tool. The approach will assist the designer to develop and prototype in a relatively short time by eliminating time consuming and error prone due to manual coding. The proposed design methodology has been applied to the well know Pertub and Observe (P&O) MPPT controller. The Matlab/Simulink model of the P&O controller is optimized and converted to target, Hardware Description Language (HDL) code for FPGA/ASIC. The whole architecture of the P&O controller has been implemented on a Xilinx Spartan 3E prototyping board. We demonstrate that the generated RTL code can be easily mapped into FPGA/ASICs, which allow the rapid prototyping of PVS with more complex algorithms.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117164040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

RF and non-linearity characterization of porous silicon layer for RF-ICs 射频集成电路中多孔硅层的射频和非线性特性

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038591

Y. Belaroussi, A. Slimane, M. Belaroussi, M. Trabelsi, G. Scheen, K. B. Ali, J. Raskin

引用次数: 4

Reliability analysis of CMOS inverter subjected to AC & DC NBTI stresses 交直流NBTI应力作用下CMOS逆变器可靠性分析

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038602

A. Chenouf, B. Djezzar, A. Benabdelmoumene, H. Tahi, M. Goudjil

引用次数: 5

Automated formal verification of X propagation with respect to testability issues 关于可测试性问题的X传播的自动形式化验证

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038596

M. Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß

引用次数: 0

iJTAG integration of complex digital embedded instruments iJTAG集成复杂数字嵌入式仪器

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-11-28 DOI: 10.1109/IDT.2014.7038580

Ahmed M. Y. Ibrahim, H. Kerkhoff

引用次数: 13

A new binary arithmetic for finite-word-length linear controllers: MEMS applications 有限字长线性控制器的一种新的二进制算法:MEMS应用

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-01-20 DOI: 10.1109/IDT.2014.7038608

A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet

{"title":"A new binary arithmetic for finite-word-length linear controllers: MEMS applications","authors":"A. K. Oudjida, A. Liacha, M. L. Berrandjia, N. Chaillet","doi":"10.1109/IDT.2014.7038608","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038608","url":null,"abstract":"This paper addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work. Because MEMS applications are targeted, the binary arithmetic must be fast enough to cope with the rapid dynamic of MEMS; power-efficient for an embedded control; highly scalable for an easy adjustment of the control performances; and easily predictable to provide a precise idea on the required logic resources before the implementation. The exploration of a number of binary arithmetics showed that radix-2r is the best candidate that fits the aforementioned requirements. It has been fully exploited to designing efficient multiplier cores, which are the real engine of the linear systems. The radix-2r arithmetic was applied to the hardware integration of two FWL structures: a linear time variant PID controller and a linear time invariant LQG controller with Kaiman filtering. Both controllers showed a clear superiority over their existing counterparts, or in comparison to their initial non-optimized forms.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"58 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125564965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1