Impact analysis of resistive bridge within deep submicron Secured CMOS circuits

Abstract

This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value. It is also shown, that the WDDL is more vulnerable than SecLib.