A UVM-based smart functional verification platform: Concepts, pros, cons, and opportunities

Abstract

SoC Verification is one of the hot issues in VLSI. More than 70 percent of the time is spent on verification. So, there is a need for constructing a reusable and robust verification environment. Universal verification methodology (UVM) is a promising solution to address these needs. This paper presents a survey on the features of UVM. It presents its pros, cons, and opportunities. Moreover, it presents simple steps to verify an IP and build an efficient verification environment. A SoC case study is presented to compare traditional verification with UVM-based verification.