深亚微米固定CMOS电路中电阻桥的冲击分析

2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI:10.1109/IDT.2014.7038597

G. A. Abdelmalek, R. Ziani

{"title":"深亚微米固定CMOS电路中电阻桥的冲击分析","authors":"G. A. Abdelmalek, R. Ziani","doi":"10.1109/IDT.2014.7038597","DOIUrl":null,"url":null,"abstract":"This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value. It is also shown, that the WDDL is more vulnerable than SecLib.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Impact analysis of resistive bridge within deep submicron Secured CMOS circuits\",\"authors\":\"G. A. Abdelmalek, R. Ziani\",\"doi\":\"10.1109/IDT.2014.7038597\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value. It is also shown, that the WDDL is more vulnerable than SecLib.\",\"PeriodicalId\":122246,\"journal\":{\"name\":\"2014 9th International Design and Test Symposium (IDT)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 9th International Design and Test Symposium (IDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDT.2014.7038597\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 9th International Design and Test Symposium (IDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2014.7038597","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文在安全电路测试和相关故障模型表征领域迈出了第一步。我们分析了在WDDL和SecLib中实现的深亚微米安全电路中电阻桥缺陷的电学影响。SPICE仿真验证了该分析的质量。结果表明，缺陷的检测依赖于桥接电阻值。研究还表明，WDDL比SecLib更脆弱。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact analysis of resistive bridge within deep submicron Secured CMOS circuits

This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value. It is also shown, that the WDDL is more vulnerable than SecLib.

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2014 9th International Design and Test Symposium (IDT)

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