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2014 9th International Design and Test Symposium (IDT)最新文献

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Translating of MATLAB/SIMULINLK model to synchronous dataflow graph for parallelism analysis and programming embedded multicore systems MATLAB/ simulink模型转换成同步数据流图，用于并行分析和嵌入式多核系统编程
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038605
K. Guesmi, S. Hasnaoui
{"title":"Translating of MATLAB/SIMULINLK model to synchronous dataflow graph for parallelism analysis and programming embedded multicore systems","authors":"K. Guesmi, S. Hasnaoui","doi":"10.1109/IDT.2014.7038605","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038605","url":null,"abstract":"Software implementation of compute-intensive applications in digital signal processing requires large computing power and has real-time performance requirements. Employing multicore architecture is usually the only means for solving the grand challenge of computational problems. Developing multicore-based systems requires a high degree of concurrency for optimizing performances of systems. For this purpose, this paper addresses the redesigning of MATLABSimulink models for efficient concurrent implementation using multiple processors. Our approach consists of translating a Simiüink model into discrete synchronous dataflow graph in order to treat them as concurrent system by exploiting task-level parallelism without alter the input-output behavior of the system.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High speed special function unit for graphics processing unit 高速图形处理专用单元
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038581
Abd-Elrahman G. Qoutb, Abdullah M. El-Gunidy, M. Tolba, M. El-Moursy
{"title":"High speed special function unit for graphics processing unit","authors":"Abd-Elrahman G. Qoutb, Abdullah M. El-Gunidy, M. Tolba, M. El-Moursy","doi":"10.1109/IDT.2014.7038581","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038581","url":null,"abstract":"A fixed-point ASIC design for high-speed, second-order, piecewise function approximation is presented. A Non-Uniform segmentation method based on Minimax approximation is used to get the interpolation coefficients. Non-Uniform segmentation, effectively, reduces the size of the coefficient table with a small area overhead for the address encoder. The proposed algorithm truncates the binary coefficients within the pre-al located error. Radix-eight Booth multipliers are used to reduce the number of partial products to, around one third of the traditional multiplication, hence speeding up the evaluation process. Very fast reduction trees with four-to-two compressors are used to reduce the number of the resulting partial products. Also, a new radix-eight sign template which reduces the overall area of the multipliers is proposed. Hybrid carry-look ahead, carry-ripple adders are, also, used. The design has been verified on FPGA Moreover, 45nm PDK is used to synthesize and layout the design. A maximum propagation delay of 5.251ns is achieved with a reduction of 19% in the total delay as compared to other traditional methods. A total chip area of 0.014mm2 is also achieved.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131248176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Early reliability evaluation of a biomédical system 生物医学系统的早期可靠性评估
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038585
H. Hakobyan, P. Rech, M. Reorda, M. Violante
{"title":"Early reliability evaluation of a biomédical system","authors":"H. Hakobyan, P. Rech, M. Reorda, M. Violante","doi":"10.1109/IDT.2014.7038585","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038585","url":null,"abstract":"Early reliability evaluation for safety-critical applications is crucial, since it may allow to spot critical parts of the design and to introduce suitable countermeasures. In some domains it is common to adopt a design flow exploiting a high-level description of the system behavior and architecture; out of this description, suitable tools then automatically generate the software (and eventually the hardware) needed to perform the required tasks. This paper describes an enhanced version of such a design flow in which reliability is also considered and evaluated. The model of a pacemaker is developed and used for early estimation of its robustness with respect to a subset of the possible faults. The paper highlights why it is important to take into account the environment the target system is designed to interact with (in this case the heart), thus making possible to identify the most critical faults, based on the severity of their effects.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131273972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Formal verification of AUTOSAR FlexRay state manager AUTOSAR FlexRay状态管理器的正式验证
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038612
G. Bahig, A. El-Kadi, A. Salem
{"title":"Formal verification of AUTOSAR FlexRay state manager","authors":"G. Bahig, A. El-Kadi, A. Salem","doi":"10.1109/IDT.2014.7038612","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038612","url":null,"abstract":"Automotive software systems have continuously faced challenges in managing complexity associated with functional growth, flexibility of systems so that they can be easily modified, scalability of solutions across several product lines, quality and reliability of systems, and finally the ability to detect errors early in design phases. AUTOSAR was established to develop open standards to address these challenges. Formal method is one way to address the ability to detect errors and ensure compliance to requirements in early design stages. In this paper, AUTOSAR's FlexRay State Manager basic software module is formally represented in finite state machine augmented with complex data types. Specification requirements are mapped into formal model theorems and assertions. SMT solvers are utilized to validate design compliance to specification to show the possibility of detecting errors early in the design phase via mapping AUTOSAR's specification into formal design notation.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115977503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new efficient reduction scheme to implement tree multipliers on FPGAs 在fpga上实现树乘法器的一种新的高效简化方案
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038609
K. Mhaidat, Abdulmughni Y. Hamzah
{"title":"A new efficient reduction scheme to implement tree multipliers on FPGAs","authors":"K. Mhaidat, Abdulmughni Y. Hamzah","doi":"10.1109/IDT.2014.7038609","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038609","url":null,"abstract":"Fast multipliers are essential for many applications such as digital signal processing (DSP) and image and video processing. Tree parallel multipliers are the fastest ones. The only disadvantage of tree multipliers over serial multipliers is its high cost in terms of area and power dissipation. In this paper, we present a new efficient reduction scheme to implement tree multipliers on field programmable gate arrays (FPGAs) in a way that is more suitable for the lookup tables (LUTs) structure in FPGAs. The scheme is based on using a library of m.n counters. The aim of this scheme is to minimize the number of reduction steps to maximize reduction ratio which in turn reduces area and delay. A script was written to automate Verilog code generation according to the proposed scheme. Simulation and synthesis were conducted using Xilinx ISE suite. Results show that our scheme needs 13.4% and 32.6% less LUTs than the well-known Dadda and Wallace reduction tree schemes, respectively. Also, the delay is less by 44.8% and 52.8% than Dadda and Wallace schemes, respectively.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127386766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Exploiting satisfiability modulo theories for analog layout automation 利用可满足模理论实现模拟布局自动化
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038590
S. Saif, M. Dessouky, S. Nassar, H. Abbas, M. El-Kharashi, Mohammad Abdulaziz
{"title":"Exploiting satisfiability modulo theories for analog layout automation","authors":"S. Saif, M. Dessouky, S. Nassar, H. Abbas, M. El-Kharashi, Mohammad Abdulaziz","doi":"10.1109/IDT.2014.7038590","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038590","url":null,"abstract":"This paper explores the use of Satisfiability Modulo Theories to handle mirror symmetry and common-centroid analog layout placement constraints. The proposed system reads the constraints and generates the corresponding equations or inequalities needed for Microsoft Z3 solver. These inequalities are resolved using quantifier free nonlinear real arithmetic theory. This theory has doubly exponential complexity in the worst case and it guarantees generating a solution if one exists. The proposed system produces multiple layouts that satisfy the constraints and allows the designer to choose the appropriate one according to designer's experience.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-cost EVM built-in test of RF transceivers 射频收发器的低成本EVM内置测试
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038586
A. Serhan, L. Abdallah, H. Stratigopoulos, S. Mir
{"title":"Low-cost EVM built-in test of RF transceivers","authors":"A. Serhan, L. Abdallah, H. Stratigopoulos, S. Mir","doi":"10.1109/IDT.2014.7038586","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038586","url":null,"abstract":"We present a novel low-cost built-in test approach for the Error Vector Magnitude (EVM) performance of RF transceivers. We rely on built-in sensors to extract low-cost measurements that can be used thereafter to predict implicitly the EVM. The key attribute of the sensors is that they are non-intrusive, that is, they are not electrically connected to the RF transceiver. Hence, the proposed built-in test approach does not necessitate any design modifications in the RF transceiver. The sensors provide measurements that track process variations and, thereby, they can predict drifts in the EVM value that are due to such process variations. Simulation results demonstrate that the proposed built-in test predicts the EVM with less than 6% error.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131714105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling sequential circuits with shared structurally synthesized BDDs 基于共享结构合成bdd的顺序电路建模
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038600
R. Ubar, M. Marenkov, Dmitri Mironov, V. Viies
{"title":"Modeling sequential circuits with shared structurally synthesized BDDs","authors":"R. Ubar, M. Marenkov, Dmitri Mironov, V. Viies","doi":"10.1109/IDT.2014.7038600","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038600","url":null,"abstract":"A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the property of one-to-one mapping between the nodes in the graph and signal paths in the corresponding sequential circuit. A method is proposed for synthesis of S BDDs from the given sequential circuit, which produces as side-effect the collapsed set of fault sites both for stuck-at and delay faults. Thanks to the model compression, the increased speed of simulation and fault reasoning is expected. Experimental results demonstrate the advantages of the new model in terms of size, reduced fault set and estimated fault simulation speed.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integration of STT-MRAM model into CACTI simulator 将STT-MRAM模型集成到CACTI模拟器中
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038589
S. Arcaro, S. Carlo, Marco Indaco, D. Pala, P. Prinetto, E. Vatajelu
{"title":"Integration of STT-MRAM model into CACTI simulator","authors":"S. Arcaro, S. Carlo, Marco Indaco, D. Pala, P. Prinetto, E. Vatajelu","doi":"10.1109/IDT.2014.7038589","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038589","url":null,"abstract":"In the last decade, academies and private companies have actively explored emerging memory technologies. STT-MRAM in particular is experiencing a rapid development but it is facing several challenges in terms of performance and reliability. Several techniques at cell level have been proposed to mitigate such issues but currently few tools and methodologies exist to support designers in evaluating the impact that specific micro-level design choices can determine on the STT-MRAM macro design. In this paper we present a system-level tool based on CACTI simulator to assist memory system designers. We use our tool to generate high-performance and low-power cache memories comparing performance, energy consumption, and area with traditional SRAM.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121144408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An improved electronic voting machine using a microcontroller and a smart card 采用微控制器和智能卡的改进型电子投票机
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038617
Dichou Karima, V. Tourtchine, R. Faycal
{"title":"An improved electronic voting machine using a microcontroller and a smart card","authors":"Dichou Karima, V. Tourtchine, R. Faycal","doi":"10.1109/IDT.2014.7038617","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038617","url":null,"abstract":"In this paper, an improved electronic voting machine using a microcontroller and a smart card is presented. The identity control that was done manually is eliminated and replaced by a smart card. It also saves the elector's card number, number of electors, and the voting results while ensuring anonymity. The results are only accessible for the administrator card. The simulation is done using Proteus Professional Software V7. Microcontrollers are programmed in assembly language under MPLAB IDE software V.8.56.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115077535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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