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A high radix montgomery multiplier with concurrent error detection 具有并发错误检测的高基数蒙哥马利乘法器
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038613
Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, N. Axelos, K. Pekmestzi
{"title":"A high radix montgomery multiplier with concurrent error detection","authors":"Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, N. Axelos, K. Pekmestzi","doi":"10.1109/IDT.2014.7038613","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038613","url":null,"abstract":"Modular multiplication is essential in cryptographic algorithms (e.g. RSA), as it determines the performance of the entire cryptographic operation and its reliability is crucial for the system security. In this paper, we propose a high-radix Montgomery Modular Multiplication (MMM) implementation and conduct an exploration to find the optimal radix. Also, a concurrent error detection circuit with 99.9% detection rate, small area and power overheads (2.24% and 1.46% respectively) is proposed to protect the MMM against fault attacks and natural faults.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127695863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reaction-diffusion model for interface traps induced by BTS stress including H+, H and H2 as diffusion species 以H+、H和H2为扩散种的BTS应力诱导界面陷阱反应扩散模型
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038619
M. Boubaaya, H. Tahi, B. Djezzar, Karim Benmassai, A. Benabdelmoumene, M. Goudjil, D. Doumaz, Abdelhak Feraht Hemida
{"title":"Reaction-diffusion model for interface traps induced by BTS stress including H+, H and H2 as diffusion species","authors":"M. Boubaaya, H. Tahi, B. Djezzar, Karim Benmassai, A. Benabdelmoumene, M. Goudjil, D. Doumaz, Abdelhak Feraht Hemida","doi":"10.1109/IDT.2014.7038619","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038619","url":null,"abstract":"Negative and positive bias temperature instability (NBTI and PBTI) are described in the same model using the Reaction-Diffusion (RD) by taking into account all protagonist diffusion hydrogenate species; hydrogen atom (H), proton (H+) and hydrogen molecular (H2). This model is based on the probability that the passivated dangling bonds at the interface of silicon-oxide release the hydrogen H or proton H+. This probability is expressed as a function of experimental parameters.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ZnO based gas sensor testing 基于ZnO的气体传感器测试
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038604
Y. Bakha, Y. Djeridane, W. Aouimeur, Lamia Menasri, A. Smatti, S. Hamzaoui
{"title":"ZnO based gas sensor testing","authors":"Y. Bakha, Y. Djeridane, W. Aouimeur, Lamia Menasri, A. Smatti, S. Hamzaoui","doi":"10.1109/IDT.2014.7038604","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038604","url":null,"abstract":"This paper describes and presents an initial test result of ZnO based gas sensor applied to ethanol vapour detection. Intrinsic ZnO and Al (1 %) doped AZO thin films are deposited on SiO2/Si substrate by spray pyrolysis method with in-situ optimised heater. X-ray diffraction analysis revealed that all the films are polycrystalline with c(002)-axis orientation wurtzite structure normal to the substrate surface. Test sensor detection was performed at operating temperature of 240°C for 100 ppm and 300 ppm of ethanol gas. A net resistance decreasing is obtained in response about three orders of magnitude.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126291801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Accurate analog/RF BIST evaluation based on SVM classification of the process parameters 基于支持向量机工艺参数分类的精确模拟/射频BIST评价
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038587
A. Bounceur, B. Brahmi, Kamel Beznia, R. Euler
{"title":"Accurate analog/RF BIST evaluation based on SVM classification of the process parameters","authors":"A. Bounceur, B. Brahmi, Kamel Beznia, R. Euler","doi":"10.1109/IDT.2014.7038587","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038587","url":null,"abstract":"The analog/RF functional test which is based on specification circuit testing is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-in Self Test (BIST) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage by estimating the Test Escapes (Te) and the Yield Loss (Yl). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. A necessary number of these circuits cannot be obtained with a Monte Carlo simulation alone. Statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. The development of Extreme Value Theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, this theory is very complex and difficult to apply in the case of multivariate problems. In this paper, we propose an improvement of this approach. The classification of the circuits is based on the specifications and the test limits instead of the extreme thresholds and no post-classification simulation is necessary. Also, we illustrate the use of this model for the evaluation of a filter BIST technique.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126785188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High performance MAC designs 高性能MAC设计
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038582
Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, K. Pekmestzi, C. Efstathiou
{"title":"High performance MAC designs","authors":"Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, K. Pekmestzi, C. Efstathiou","doi":"10.1109/IDT.2014.7038582","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038582","url":null,"abstract":"In this paper we propose two high performance multiplication-accumulation (MAC) designs. Targeting to operate at higher frequency, we investigate two different techniques based on the carry-save representation in order to reduce the delay impact of the accumulation process on the MAC operation. We conducted detailed experimental measurements to verify the advantages of the proposed MAC designs compared to two existing ones. Both the proposed designs operate at higher frequency without any losses in the area occupied or the power consumed.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RF filter characterization using a chirp 使用啁啾的射频滤波器特性
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038576
Peter Sarson
{"title":"RF filter characterization using a chirp","authors":"Peter Sarson","doi":"10.1109/IDT.2014.7038576","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038576","url":null,"abstract":"Historically test engineers have had the problem that during debug of initial silicon that they are asked to characterize certain parts of the device. This adds time pressure as this is never part of the test quotation which also adds cost pressure since this takes extra test time and tester time to develop. The following topic will discuss a simple to develop method that will characterize a filter using a chirp to sweep the filters' frequency range. The Digital Signal Processing (DSP) behind this will also be covered.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129480567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
BDD based synthesis of Boolean functions using memristors 基于记忆电阻器的布尔函数合成
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038601
Sayak Chakraborti, Paturi Varun Chowdhary, K. Datta, I. Sengupta
{"title":"BDD based synthesis of Boolean functions using memristors","authors":"Sayak Chakraborti, Paturi Varun Chowdhary, K. Datta, I. Sengupta","doi":"10.1109/IDT.2014.7038601","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038601","url":null,"abstract":"Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124587466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Design for security test on cryptographic ICs for design-time security evaluation 用于设计时安全性评估的加密集成电路安全测试设计
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038598
C. Shao, Huiyun Li, Guoqing Xu, X. Hu
{"title":"Design for security test on cryptographic ICs for design-time security evaluation","authors":"C. Shao, Huiyun Li, Guoqing Xu, X. Hu","doi":"10.1109/IDT.2014.7038598","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038598","url":null,"abstract":"Cryptographic ICs are facing a serious threat of fault injection attacks. However, the security test nowadays is still sample test instead of volume test, exploiting workload statistics and experiences as qualitative indexes. This paper proposes a design for test method, to facilitate fast and automatic security test of cryptographic ICs. First we identify the sensitive registers crucial to the fault injection, and the secret key related registers are carefully isolated out of the marked registers. Next, the scan chains are inserted onto the marked registers and the test pattern is generated. Finally, the cryptographic IC is evaluated in test mode with fault injection simulation, and the simulation result will be compared to the golden reference pattern. Any inconsistency indicates the crypto chip will fail in the security test. The reported faulty chains and cells could locate the weaknesses accurately. The case study on a CRT-RSA implementation proves the feasibility of the proposed method, with negligible hardware overhead. The method can be easily extended to other cryptographic algorithms.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TSV-based 3D integration fabrication technologies: An overview 基于tsv的三维集成制造技术综述
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038623
K. Salah
{"title":"TSV-based 3D integration fabrication technologies: An overview","authors":"K. Salah","doi":"10.1109/IDT.2014.7038623","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038623","url":null,"abstract":"3D Integration is a promising and attractive solution for interconnect bottleneck problem, transistor scaling physical limitations, and impractical small-scale lithography. 3D integration extends Moore's law in the third dimension, offering heterogeneous integration, higher density, lower power consumption, and faster performance. However, in order to fabricate 3D ICs, new capabilities are needed: process technology, physical modeling, physical design tools, 3D architectures, design methods and tools. The goal of this paper is to cover the manufacturability of TSV-based 3D-ICs Le. process technology, and fabrication capability.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Computational complexity in test-generation algorithms 测试生成算法的计算复杂度
2014 9th International Design and Test Symposium (IDT) Pub Date : 2014-12-01 DOI: 10.1109/IDT.2014.7038599
J. Sziray
{"title":"Computational complexity in test-generation algorithms","authors":"J. Sziray","doi":"10.1109/IDT.2014.7038599","DOIUrl":"https://doi.org/10.1109/IDT.2014.7038599","url":null,"abstract":"The paper is concerned with analyzing and comparing two exact algorithms from the viewpoint of computational complexity. Both serve for calculating fault-detection tests of digital circuits. The first one is the so-called composite justification, and the second is the D-algorithm. The analysis will be performed on combinational logic networks at the gate level. Here single and multiple stuck-at logic faults will be considered. As a result, it is pointed out that the composite justification requires significantly less computational step than the D-algorithm and its modifications. The difference manifests itself especially in terms of multiple faults. From this fact it has been conjectured that possibly no other algorithm is available in this field with fewer computational steps. If the claim holds, then it follows directly that the test-calculation problem is of exponential time, and so are all the other NP-complete problems. It may also be expected that the minimal complexity of composite justification applies to any modeling level (either low or high) of digital circuits, just like the exponential-time solution.","PeriodicalId":122246,"journal":{"name":"2014 9th International Design and Test Symposium (IDT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130696754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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