Modeling sequential circuits with shared structurally synthesized BDDs

A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the property of one-to-one mapping between the nodes in the graph and signal paths in the corresponding sequential circuit. A method is proposed for synthesis of S BDDs from the given sequential circuit, which produces as side-effect the collapsed set of fault sites both for stuck-at and delay faults. Thanks to the model compression, the increased speed of simulation and fault reasoning is expected. Experimental results demonstrate the advantages of the new model in terms of size, reduced fault set and estimated fault simulation speed.