Enhanced bit-width optimization for linear circuits with feedbacks

Abstract

Bit widths to accuracy trade offs require complex method development and testing. This paper presents a new process of incremental optimizations to get to reduced bit-widths compared to recently published results. Range and Precision improvements reach all the data path interconnections. More, a precision refinement is proposed even for input data. Detailed procedures and results of hardware implementations are provided to show the achieved improvements compared to existing optimization approaches. For illustration and to compare our work to existing results, different configurations of an IIR filter is used for tests and implementations. Depending on those different configurations, the proposed optimization techniques present an average of area reductions ranging from 17% to 30%.