Scalable high speed serial interface for data converters: Using the JESD204B industry standard

Abstract

The need for wideband data converters (DAC and ADC) with increasingly higher sampling frequencies and data resolutions are driven by new applications, as well as advances in existing ones. The bandwidth limitations of current I/O technologies, such as CMOS or LVDS, force the need for higher pin counts on converter products. The JESD204 standard interface offers several advantages over its CMOS and LVDS predecessors in term of speed, power, size, cost, and scalability. In this paper we present a systematic approach that facilitates the adoption of the new high speed serial interface starting from system level constraints. We describe how to handle some key design features like higher data bandwidth, multi-device synchronization, deterministic latency, and harmonic clocking that are required by high data rate end-system applications such as wireless infrastructure transceivers.