用于多标准无线应用的0.9 V低功耗可重构CMOS折叠级联电路

A. Taibi, A. Slimane, Sid-Ahmed Tedjini-Bailiche, M. Belaroussi, D. Maafri, M. Trabelsi
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引用次数: 2

摘要

本文提出了一种可重构的CMOS折叠级联电路,适用于GSM (PCS1900)、3G (UMTS)、蓝牙和WLAN b/g等多标准无线应用。基于低电压应用的感应退化折叠级联码拓扑,所提出的LNA在良好的增益、噪声系数和功耗之间取得了很好的平衡。输入输出匹配网络包括电容开关装置,用于控制多标准的频段选择。采用0.13 μm CMOS工艺实现的仿真结果显示,该电路的最大功率增益为20.82 dB,噪声系数低于1.72 dB,输入和输出回波损耗分别小于-14 dB和-15 dB。在2.4 GHz的输入频率下,LNA的最小三阶输入截距为-15 dBm。对于所有标准,建议的LNA在0.9 V电源电压下仅消耗5.15 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.9 V low power reconfigurable CMOS folded cascode LNA for multi-standard wireless applications
In This paper, a reconfigurable CMOS folded cascode LNA for multi-standard wireless applications is presented, including GSM (PCS1900), 3G (UMTS), Bluetooth and WLAN b/g. Based on inductive degenerated folded-cascode topology for low voltage applications, the proposed LNA achieves a good trade-off between good gain, noise figure and power consumption. The input and output matching networks include capacitor switches devices to control the band selection for multi-standard purpose. Implemented in 0.13-μm CMOS technology, the simulated results perform a maximum power gain of 20.82 dB, a noise figure below 1.72 dB, an input and output return loss less than -14 dB and -15 dB, respectively. The LNA achieves -15 dBm of a minimum third-order input intercept point at input frequency of 2.4 GHz. For all standards the proposed LNA consumes only 5.15 mW from 0.9 V supply voltage.
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