An independent dual gate SOI FinFET soft-error resilient memory cell

Abstract

In this paper we present an 8T footless storage element, the FFDICE (FinFET DICE), a dual interlocked structure using Independent Gate SOI FinFET transistors that exhibits soft error resilience characteristics. Compared to the conventional DICE cell, the proposed design achieves area savings by dispensing with the four NMOS driver transistors, retains the excellent tolerance characteristics to single node upsets and similar multiple node upset resilience. Of significance to modern designs that apply voltage scaling techniques to achieve power savings, simulation results on Static Voltage Noise Margin and Static Current Noise Margin metrics show that the proposed cell exhibits excellent stability across an examined voltage range of 0.75V to 1V.