Multi-device layout templates for nanometer analog design

With the advance of nanoscale fabrication processes, well-known common-centroid analog layout techniques are no longer sufficient to guarantee the required level of device matching. This paper proposes a complex multi-device layout generator of highly matched devices for analog circuit design. The proposed tool offers different placement techniques for alternative layouts, as well as different matching strategies with focus on common-centroid, lithography and stress effect mitigation. Device arrays are key for producing uniform, litho-friendly layouts. Generic array templates can be generated for transistors, resistors and capacitors. The layout of a switched-capacitor integrator is given as an example.