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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)最新文献

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A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction 一个66db SNDR流水线分流adc，采用ab类剩余放大器和模拟增益校正
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313890
Md Shakil Akter, R. Sehgal, Frank M. L. van der Goes, K. Bult
{"title":"A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction","authors":"Md Shakil Akter, R. Sehgal, Frank M. L. van der Goes, K. Bult","doi":"10.1109/ESSCIRC.2015.7313890","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313890","url":null,"abstract":"This paper proposes a class-AB residue amplifier topology that significantly improves the power efficiency of residue amplification. Due to its inherent high linearity, the amplifier can be allowed to have a reduced settling to further enhance its power efficiency while still maintaining the required linearity performance. Moreover, it enables an efficient way of correcting gain errors in the analog domain by simply tuning the bias current, without requiring any additional analog power. The digital power for calibration also becomes negligible, since the detection of gain errors can be done digitally at a slow rate. The calibration of the prototype pipelined split-ADC in a 40nm CMOS reaches convergence in only 12×103 clock cycles. The ADC achieves more than 10.3b ENOB near Nyquist input up to 106 MS/s clock speed. At 53 MS/s clock with close to Nyquist-frequency input, the ADC demonstrates an SNDR and SFDR of 66 dB and 77.3 dB respectively while consuming 9 mW of power, of which the residue amplifiers consume only 0.83 mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72636341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors 28nm FD-SOI技术和设计平台，用于低于10pj /cycle和ser免疫32位处理器
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313840
F. Abouzeid, S. Clerc, C. Bottoni, Benjamin Coeffic, J. Daveau, D. Croain, G. Gasiot, Dimitri Soussan, P. Roche
{"title":"28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors","authors":"F. Abouzeid, S. Clerc, C. Bottoni, Benjamin Coeffic, J. Daveau, D. Croain, G. Gasiot, Dimitri Soussan, P. Roche","doi":"10.1109/ESSCIRC.2015.7313840","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313840","url":null,"abstract":"This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM® Cortex®-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78027116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links 用于短距离光链路的2.5 gb /s多速率连续时间自适应均衡器
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313824
C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, J. Aguirre, C. Aldea, S. Celma
{"title":"A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links","authors":"C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, J. Aguirre, C. Aldea, S. Celma","doi":"10.1109/ESSCIRC.2015.7313824","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313824","url":null,"abstract":"This paper presents a new multi-rate continuous-time adaptive equalizer for short-haul gigabit optical communications. It is designed to compensate the attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mb/s up to 2.5 Gb/s. It includes three adaptation loops to compensate the possible variations in level and spectrum of the input signal. The prototype has been implemented in a cost-effective 0.18-μm CMOS process. The system is fed with only 1 V and has a total power consumption of 60 mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74679223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from −50°C to 150°C in a 16nm FinFET process 在16nm FinFET工艺中，误差为±2°C的3西格玛温度传感器没有从- 50°C到150°C的修整
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313879
Mei-Chen Chuang, C. Tai, Y. Hsu, A. Roth, E. Soenen
{"title":"A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from −50°C to 150°C in a 16nm FinFET process","authors":"Mei-Chen Chuang, C. Tai, Y. Hsu, A. Roth, E. Soenen","doi":"10.1109/ESSCIRC.2015.7313879","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313879","url":null,"abstract":"Two compact thermal sensors in advanced technologies are compared. One uses a 20nm planar process, while the other uses a 16nm FinFET process. Both produce a digital temperature reading through the ratiometric conversion of a temperature-dependent and a temperature-independent current. The currents are integrated on an on-chip capacitor, which forms part of a single-bit first-order continuous-time JA modulator. As a result, the modulator does not require an extra op-amp and is insensitive to process variations. The 20nm design dissipates 1.1mW, occupies 0.018 mm2 and achieves a total temperature error of +2.5°C from -25°C to 125°C using a one-point trim. For extra accuracy, the 16nm design uses Dynamic Element Matching. Realized completely with FinFET transistors, it dissipates 1.21mW, occupies 0.0126 mm2 and achieves a total error of +2°C from -50°C to 150°C without any trim.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80327583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS 6倍过采样10GS/s 60GHz极性发射机，平均PA效率15.3%
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313899
K. Khalaf, V. Vidojkovic, J. Long, P. Wambacq
{"title":"A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS","authors":"K. Khalaf, V. Vidojkovic, J. Long, P. Wambacq","doi":"10.1109/ESSCIRC.2015.7313899","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313899","url":null,"abstract":"A polar TX based on a 10GSample/s RF-DAC aimed at 802.11ad applications realizes more than 30dB alias attenuation and exceeds 3GHz input bandwidth with 6x oversampling factor. The PA drain efficiency is 29.8% with a Psat of 10.8dBm. Average TX output power is 5.3dBm with 15.3% PA efficiency running QPSK at 3.3Gb/s datarate and -23.6dB EVM. Corresponding 16-QAM values are: 3.6dBm with 11.6% at 6.7Gb/s and -18.1dB EVM. The 0.18mm2 TX core in 40nm bulk-CMOS consumes 40.2mW from 0.9V.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75376766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
0.13μm CMOS 230Mbps 21pJ/b UWB-IR transmitter with 21.3% efficiency 0.13μm CMOS 230Mbps 21pJ/b UWB-IR发射机，效率21.3%
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313900
N. Soltani, Hossein Kassiri, Hamed Mazhab-Jafari, K. Abdelhalim, R. Genov
{"title":"0.13μm CMOS 230Mbps 21pJ/b UWB-IR transmitter with 21.3% efficiency","authors":"N. Soltani, Hossein Kassiri, Hamed Mazhab-Jafari, K. Abdelhalim, R. Genov","doi":"10.1109/ESSCIRC.2015.7313900","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313900","url":null,"abstract":"An ultra-wide-band impulse-radio (UWB-IR) transmitter for low-energy implantable and wearable biomedical microsystems is presented. The transmitter provides a power-efficient high-data-rate wireless link within the 3-5 GHz band. It yields an overall power efficiency of 21.3% at data-rate of 230Mbps while consuming 21pJ per bit. The transmitted UWB pulse train is recovered at the receiver with less than 10-6 bit-error-rate (BER) measured at a distance of 1m without any pulse averaging. The chip is implemented in a 130nm CMOS technology and has an average power consumption of 3.7mW.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85854417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays 一个19.2 mw, 81.6 db SNDR, 4 mhz带宽带移位环路延迟的delta-sigma调制器
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313867
Xin Meng, Jinzhou Cao, Tao He, Yi Zhang, G. Temes, M. Aniya, Kazuki Sobue, K. Hamashita
{"title":"A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays","authors":"Xin Meng, Jinzhou Cao, Tao He, Yi Zhang, G. Temes, M. Aniya, Kazuki Sobue, K. Hamashita","doi":"10.1109/ESSCIRC.2015.7313867","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313867","url":null,"abstract":"A third-order switched-capacitor low-distortion delta-sigma ADC with shifted loop delays (SLD) is described, and its performance is discussed. It can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the last stage adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and -95.6 dB THD in a signal bandwidth of 4 MHz. It dissipates 19.2 mW with a 1.6 V power supply. The conventional low-distortion ADC was also implemented on the same chip for comparison. The new circuit has superior performance, and dissipates 25% less power (19.2 mW vs. 24.9 mW) than the conventional one. The figure-of-merit for the ADC with SLD is among the best reported for wideband discrete-time ADCs, and is almost 40% better than that of the conventional ADC.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87259994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optical wireless receiver circuit with integrated APD and high background-light immunity 集成APD和高背景光抗扰度的光无线接收电路
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313825
P. Brandl, R. Enne, H. Zimmermann
{"title":"Optical wireless receiver circuit with integrated APD and high background-light immunity","authors":"P. Brandl, R. Enne, H. Zimmermann","doi":"10.1109/ESSCIRC.2015.7313825","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313825","url":null,"abstract":"This paper presents two different monolithically integrated optoelectronic receiver circuits in one chip. One circuit includes a 200 μm diameter, high responsivity avalanche photodiode with a highly-sensitive receiver for wireless optical data communication at a data rate of 1Gbps with a sensitivity of -31.8 dBm. The second circuit includes two PN-photodiodes and a differential TIA with a nonlinear feedback to detect light power differences down to -90 dBm. The second circuit is implemented twice: for beam positioning in x- and y-direction. The chip was fabricated in a 0.35 μm high-voltage CMOS technology and tested under strong background-light conditions representative for optical wireless communication scenarios.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78174290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection 一种多模CT ΔΣ-modulator，具有可重构数字反馈滤波器，用于半数字阻塞/干扰抑制
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313868
R. Ritter, Patrick Torta, Lukas Dörrer, A. Giandomenico, S. Herzinger, M. Ortmanns
{"title":"A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection","authors":"R. Ritter, Patrick Torta, Lukas Dörrer, A. Giandomenico, S. Herzinger, M. Ortmanns","doi":"10.1109/ESSCIRC.2015.7313868","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313868","url":null,"abstract":"This paper presents a multimode-mode filtering ΔΣ-modulator for receivers with reconfigurable digitally enhanced blocker rejection. The required signal to noise ratio of the signal of interest is typically much lower than the required DR due to also received interfering signals. Therefore, it is of interest to build the ADC in the receiver with a high blocker tolerance, to reduce its required signal to noise ratio and even relax the rest of the receiver chain. For this purpose, a semi-digital implementation of a reconfigurable and frequency selective interferer suppression is proposed. The prototype is designed in a 28nm CMOS technology, occupies an area of 0.089mm2 and achieves 59.4/57.9/50.4dB inband SNDR in a bandwidth of 8.9/18.3/38.3MHz, together with a power consumption of 12.5/14.3/15.6mW. Using the proposed technique, the modulator simultaneously achieves a out-of-band blocker tolerance which is even +18dB beyond full scale.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82589951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Continuous-time hybrid computation with programmable nonlinearities 可编程非线性连续时间混合计算
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313881
Ning Guo, Yipeng Huang, T. Mai, Sharvil Patil, Chi Cao, Mingoo Seok, S. Sethumadhavan, Y. Tsividis
{"title":"Continuous-time hybrid computation with programmable nonlinearities","authors":"Ning Guo, Yipeng Huang, T. Mai, Sharvil Patil, Chi Cao, Mingoo Seok, S. Sethumadhavan, Y. Tsividis","doi":"10.1109/ESSCIRC.2015.7313881","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313881","url":null,"abstract":"We present the first continuous-time hybrid computing unit in 65nm CMOS, capable of solving nonlinear differential equations up to 4th order, and scalable to higher orders. Arbitrary nonlinear functions used in such equations are implemented by a programmable clockless continuous-time 8b hybrid architecture (ADC+SRAM+DAC) with activity-dependent power dissipation. We also demonstrate the use of the unit in a low-power cyber-physical systems application.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76902284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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