ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)最新文献_第7页

An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters 一种用于静电能量收集器的超低功率电容极值和比值检测器

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313873

B. Saft, Eric Schaefer, Alexander Rolapp, E. Hennig

{"title":"An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters","authors":"B. Saft, Eric Schaefer, Alexander Rolapp, E. Hennig","doi":"10.1109/ESSCIRC.2015.7313873","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313873","url":null,"abstract":"We present a novel ultra-low power capacitance extrema and modulation ratio detector for electrostatic micro vibration energy harvesters. The circuit signals the points in time where a varying harvester capacitance Cn(t) reaches its minimum and maximum values o min and o max in each oscillation period. A novel feature is that the circuit allows the capacitance modulation ratio ac = Cmax/Cmin between two consecutive extrema to be determined digitally. Using a self-clocked charge pumping scheme implemented with two low-power comparators and a pulse generator, our detector circuit keeps the voltage across a dedicated sense capacitor within a predefined margin around a fixed reference level. Transitions through capacitance extrema are indicated by polarity reversals of the charge packets. The number of charge packets transferred between two polarity reversals is nonlinearly but uniquely related to ac. The proposed circuit was implemented and fabricated in a commercial 0.35-/xm CMOS process. Measurements were performed using a rotating capacitor with Cmax = 150 pF and adjustable ac spinning with up to 110 Hz. Transitions through capacitance extrema were measured for ac = 1.3 ... 4.4 and were signalled accurately within the systematic time resolution limits of the method. In the presented configuration, the circuit draws a current of 60 nA from a 3.8-V supply.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89223402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW 一种5.1mW 74dB DR CT ΔΣ调制器，带量化器固有场域补偿，可实现75fJ/conv。-step in a 20MHz BW

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313865

Chongjun Ding, Y. Manoli, M. Keller

引用次数: 3

A single chip laser radar receiver with a 9×9 SPAD detector array and a 10-channel TDC 单芯片激光雷达接收机，具有9×9 SPAD探测器阵列和10通道TDC

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313903

S. Jahromi, Jussi-Pekka Jansson, I. Nissinen, J. Nissinen, J. Kostamovaara

引用次数: 13

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs 超低功耗adpll数字-时间转换器的设计和内置特性

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313882

Peng Chen, Xiongchuan Huang, Yao-Hong Liu, M. Ding, Cui Zhou, A. Ba, K. Philips, H. D. Groot, R. Staszewski

引用次数: 12

A 0.01 mm2 fully-differential 2-stage amplifier with reference-free CMFB using an architecture-switching-scheme for bandwidth variation 一个0.01 mm2的全差分2级放大器，采用无参考CMFB，采用架构切换方案，用于带宽变化

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313883

M. Kuhl, Y. Manoli

引用次数: 12

A Continuous-Time Collocated Force-Feedback and Readout Front-End for MEM Gyroscopes MEM陀螺仪的连续时间并置力反馈和读出前端

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313914

S. Nessler, M. Marx, M. Maurer, S. Rombach, Y. Manoli

引用次数: 9

32-Channel low-noise lock-in ASIC for non-invasive light detection in silicon photonics 用于硅光子学中非侵入性光检测的32通道低噪声锁定ASIC

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313904

P. Ciccarella, M. Carminati, G. Ferrari, F. Morichetti, M. Sampietro

引用次数: 0

Non-trimmable LC oscillator for all CMOS frequency control 非可调LC振荡器的所有CMOS频率控制

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313848

Philipp Greiner, J. Grosinger, C. Steffan, G. Holweg, W. Bösch

{"title":"Non-trimmable LC oscillator for all CMOS frequency control","authors":"Philipp Greiner, J. Grosinger, C. Steffan, G. Holweg, W. Bösch","doi":"10.1109/ESSCIRC.2015.7313848","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313848","url":null,"abstract":"A fully integrated all CMOS oscillator frequency reference is presented that is suitable for crystal replacement in relaxed requirement applications. The frequency reference constitutes a new approach of CMOS frequency control based on a reference-less non-trimmable LC oscillator (LCO) with a resonance frequency of approximately 3.15 GHz and a low jitter fractional divider. The fractional frequency divider consists of an integer divider and a programmable delay and thus provides a wide range of possible output frequencies from 1 to 180 MHz. A complex control logic comprising a nonvolatile memory (NVM) performs the calibration, frequency setup, and temperature compensation of the device. A planar magnetic decoupling structure is used to reduce the sensitivity of the LCO to its environment. This implementation allows the assembly of the LCO chip in a standard plastic package without using a Faraday shield. The device achieves an initial frequency stability of ±50 ppm over a temperature region of -20 to 85°C. The presented architecture overall dissipates 6.5mA from a 1.8-3.6V power supply (buffer neglected) and is competitive to already existing integer divider based LCO frequency reference realisations.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82465524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC 一个23fJ/ convstep 12b 290MS/s时间交错流水SAR ADC

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313891

Sameer Singh, M. Govindarajan, T. Venkatesh, W. Evans, A. Kansal, S. S. Murali

引用次数: 1

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular 一种28 ghz分数n频率合成器，具有参考和倍频器，用于5G蜂窝

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI: 10.1109/ESSCIRC.2015.7313832

T. Siriburanon, Hanli Liu, K. Nakata, W. Deng, J. Son, D. Lee, K. Okada, A. Matsuzawa

引用次数: 20