A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction

Abstract

This paper proposes a class-AB residue amplifier topology that significantly improves the power efficiency of residue amplification. Due to its inherent high linearity, the amplifier can be allowed to have a reduced settling to further enhance its power efficiency while still maintaining the required linearity performance. Moreover, it enables an efficient way of correcting gain errors in the analog domain by simply tuning the bias current, without requiring any additional analog power. The digital power for calibration also becomes negligible, since the detection of gain errors can be done digitally at a slow rate. The calibration of the prototype pipelined split-ADC in a 40nm CMOS reaches convergence in only 12×103 clock cycles. The ADC achieves more than 10.3b ENOB near Nyquist input up to 106 MS/s clock speed. At 53 MS/s clock with close to Nyquist-frequency input, the ADC demonstrates an SNDR and SFDR of 66 dB and 77.3 dB respectively while consuming 9 mW of power, of which the residue amplifiers consume only 0.83 mW.