28nm FD-SOI技术和设计平台，用于低于10pj /cycle和ser免疫32位处理器

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313840

F. Abouzeid, S. Clerc, C. Bottoni, Benjamin Coeffic, J. Daveau, D. Croain, G. Gasiot, Dimitri Soussan, P. Roche

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引用次数: 12

摘要

本文介绍了在28nm FD-SOI上进行的技术和设计优化，以达到ARM®Cortex®-M4 32位处理器的超低能耗和/或软误差容忍。在0.5V/45MHz工作时，测量到每周期8.9pJ的效率;在1.0V/730MHz工作时，测量到在α和中子辐射下的软误差抗免疫力。这些结果是通过设计特定的标准单元、宏和时钟树架构、技术的内在性能和适应的CAD流程来实现的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors

This paper presents the technology and design optimization performed in 28nm FD-SOI to reach ultra-low energy and/or soft-error tolerance on ARM® Cortex®-M4 32bits processors. A 8.9pJ per cycle efficiency was measured while performing at 0.5V/45MHz, and a soft-error immunity was measured under alpha and neutron radiation while performing at 1.0V/730MHz. These results were achieved by the design of specific standard cells, macros and clock tree architectures, the technology intrinsic performances, and an adapted CAD flow.

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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