2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors最新文献

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High-Resolution Transmission Electron Microscopy of Interfaces between thin Nickel Layers on Si(001) After Nickel Silicide Formation under Various Annealing Conditions 不同退火条件下硅化镍形成后Si(001)上薄镍层界面的高分辨率透射电镜研究
T. Isshiki, K. Nishio, T. Sasaki, H. Harima, M. Yoshimoto, T. Fukada, W. Yoo
{"title":"High-Resolution Transmission Electron Microscopy of Interfaces between thin Nickel Layers on Si(001) After Nickel Silicide Formation under Various Annealing Conditions","authors":"T. Isshiki, K. Nishio, T. Sasaki, H. Harima, M. Yoshimoto, T. Fukada, W. Yoo","doi":"10.1109/RTP.2006.367991","DOIUrl":"https://doi.org/10.1109/RTP.2006.367991","url":null,"abstract":"Local structures of nickel silicide formed by heat treatment of a nickel layer sputtered on silicon (100) substrate were observed by high-resolution transmission electron microscopy. In the specimen as-sputtered and after heat treatment at 498K, a thin layer was found at the interface between Ni (Ni2Si) and the Si substrate. The layer was an initial phase of silicidation and seems to be non-fluorite type NiSi2. When annealed around 600K, the NiSi2 phase disappeared and a NiSi phase grew dominantly. At the interface of NiSi/Si, the crystal lattices appeared smooth, because the lattice mismatch between NiSi and Si was absorbed by lattice distortion within a few atomic layers of the interface. The Ni3Si2 and Ni2Si phases remaining in the grown NiSi layer were also identified by Fourier analysis of the lattice fringe","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fundamental Mechanisms for Reduction of Leakage Current of Silicon Oxide and Oxynitride through RTP-Induced Phonon-Energy Coupling 通过rtp诱导声子-能量耦合降低氧化硅和氮化氧漏电流的基本机制
Zhi Chen, Jun Guo, Pangleen Ong
{"title":"Fundamental Mechanisms for Reduction of Leakage Current of Silicon Oxide and Oxynitride through RTP-Induced Phonon-Energy Coupling","authors":"Zhi Chen, Jun Guo, Pangleen Ong","doi":"10.1109/RTP.2006.367989","DOIUrl":"https://doi.org/10.1109/RTP.2006.367989","url":null,"abstract":"We study the fundamental mechanisms for dramatic reduction of leakage current of silicon oxide caused by the RTP-induced phonon-energy coupling enhancement (PECE). It is shown that the Si-O bonds are strengthened after RTP and deuterium anneal through characterization of hot-electron degradation of MOS transistors. The Si-0 bonds are strengthened because the breakdown voltage of silicon oxide is increased after RTP. We also designed special pn junctions to examine Si-Si bonds. We found that the breakdown voltage of the silicon substrate is increased by 0.3 V after RTP anneal whereas it remains the same for diodes annealed in furnace with the same parameters as in RTP. The increase in breakdown voltage of silicon is due to its intrinsic properties, i.e. stronger Si-Si bonds. The strengthening of Si-Si bonds is caused by coupling of phonon energy from silicon to thin oxide","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123920231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Calibration of Low Temperature Cable-Less Lightpipe Pyrometer on the NIST PEB Test Bed Between 50 °C and 230 °C 在NIST PEB测试台上校准50°C至230°C的低温无电缆光管高温计
B. Tsai, K. Kreider, W. Kimes
{"title":"Calibration of Low Temperature Cable-Less Lightpipe Pyrometer on the NIST PEB Test Bed Between 50 °C and 230 °C","authors":"B. Tsai, K. Kreider, W. Kimes","doi":"10.1109/RTP.2006.368014","DOIUrl":"https://doi.org/10.1109/RTP.2006.368014","url":null,"abstract":"The advent of the cable-less lightpipe radiation thermometer (CLRT) has resulted in a significant improvement in the accuracy of CLRT calibrations and measurements. CLRT systems show great promise in noncontact measurements by the elimination of the uncertainties caused by the long fiber optic cables and their connections and by the extension of the spectral range to handle low temperature applications down to ambient conditions. Calibration of the CLRT at the National Institute of Standards and Technology (NIST) is performed with the water heat pipe blackbody source between 50 degC and 230 degC. In addition, the CLRT is compared to contact thermometers on a silicon wafer heated in a post-exposure bake test bed at NIST. Comparison of the CLRT with both the blackbody and thermocouple standards provide confidence in using CLRTs and allow researchers to continued research in improving the accuracy and feasibility of applying CLRTs in semiconductor processing","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131765315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hot Plate Emissivity Effect in Low Temperature Annealing 低温退火中的热板发射率效应
T. Fukada, W. Yoo
{"title":"Hot Plate Emissivity Effect in Low Temperature Annealing","authors":"T. Fukada, W. Yoo","doi":"10.1109/RTP.2006.368013","DOIUrl":"https://doi.org/10.1109/RTP.2006.368013","url":null,"abstract":"The effect of hot plate emissivity on wafer temperature was investigated using a stacked hot plate system in the temperature range of 100degC to 500degC. Aluminum was used as the hot plate material. The emissivity of the hot plates was modified by selecting appropriate machining precision, intentional surface roughening and surface oxidation (aging). As the emissivity of the hot plates increases from 0.06 (as machined aluminum) to ~0.8 (oxidized aluminum with rough surface), the wafer temperature stabilized at higher temperatures. The difference in stabilized wafer temperature increased as the hot plate temperature increased. The difference in stabilized wafer temperature between low emissivity and high emissivity hot plates, at hot plate temperatures of 200degC and 500degC, were ~20degC and ~80degC, respectively. The effect of hot plate emissivity on wafer stabilization temperature was also verified by inserting high emissivity (~0.9 in the infrared region) quartz plates between low emissivity, stacked aluminum hot plates. The emissivity enhancement of the hot plate system was effective in bringing the stabilized wafer temperature close to that of the surrounding hot plates, even at temperatures below 500degC","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114665537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pattern Effects with the Mask off... 图案效果与蒙版关闭…
Z. Nényei, J. Niess, W. Lerch, W. Dietl, P. Timans, P. Pichler
{"title":"Pattern Effects with the Mask off...","authors":"Z. Nényei, J. Niess, W. Lerch, W. Dietl, P. Timans, P. Pichler","doi":"10.1109/RTP.2006.367998","DOIUrl":"https://doi.org/10.1109/RTP.2006.367998","url":null,"abstract":"Pattern effects during RTP have been extensively studied for the last 15 years, but have only recently attained focus in device production. The detection and the evaluation of pattern effects are in most cases difficult. Different coatings on the Si wafers hinder direct measurements and indirect evaluations. Production people recognize pattern effect frequently as a malfunction in temperature control. People in process integration can not easily separate the main root cause of broader parameter distribution in electrical parameters in final test due to the overlapping results of CD variations in lithography and those of the microloading effects in RTP, CMP and plasma etch processing. In this paper the authors clarify the versatile realisations of pattern effects in different geometrical fractals and for different coating materials. The authors describe new methods for easy evaluation of pattern effects in production. An inherent solution to eliminate pattern effects in dual side heated RTP is to create a (hot) black body cavity at the frontside of the production wafer. This can be achieved by positioning an additional Si wafer (called hot shield) near the frontside of the production wafer. This arrangement allows 150 K/s ramp rate and dramatically reduces intra-die variations compared to a process where a wafer is heated without the hot shield at the same ramp up rate. The enhanced thermal mass with the hot shield results in slightly longer \"peak time\" for spike annealing. The modelling results show that the actual longer peak time can easily be compensated by slightly reduced maximum temperature and by changed implant parameters","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Progress in Ultra Thin Gate Dielecgtric for System LSI Application 用于系统LSI的超薄栅极电介质的研究进展
J. Yugami, S. Tsujikawa, M. Inoue, M. Mizutani, T. Hayashi, Y. Nishida, H. Umeda
{"title":"The Progress in Ultra Thin Gate Dielecgtric for System LSI Application","authors":"J. Yugami, S. Tsujikawa, M. Inoue, M. Mizutani, T. Hayashi, Y. Nishida, H. Umeda","doi":"10.1109/RTP.2006.367982","DOIUrl":"https://doi.org/10.1109/RTP.2006.367982","url":null,"abstract":"EOT reduction is a key challenge to keep the Moore's law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorporation is promising from reliability aspect","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-Contact, Non-Destructive Characterization of Crystal Quality in Ultra-Shallow ion Implanted Silicon Wafers Before and after Annealing 超浅离子注入硅片退火前后的非接触、非破坏性晶体质量表征
M. Yoshimoto, H. Nishigaki, H. Harima, T. Isshiki, K. Kang, W. Yoo
{"title":"Non-Contact, Non-Destructive Characterization of Crystal Quality in Ultra-Shallow ion Implanted Silicon Wafers Before and after Annealing","authors":"M. Yoshimoto, H. Nishigaki, H. Harima, T. Isshiki, K. Kang, W. Yoo","doi":"10.1109/RTP.2006.367993","DOIUrl":"https://doi.org/10.1109/RTP.2006.367993","url":null,"abstract":"Ultraviolet (UV) Raman scattering spectroscopy provides new insight into the recrystallization process versus depth in the ultra-shallow ion-implanted layer not provided by conventional characterization techniques. The recrystallization process in ultra-shallow B-implanted layers on silicon was characterized by Raman scattering spectroscopy under UV excitation. To recrystallize damaged layers after ion implantation, rapid annealing processes were carried out in both a millisecond flash annealing system and a spike annealing system. The effectiveness of this anneal is compared to Raman evaluation of non-USJ, B-implanted layers with hundred nanometer scale depth thoroughly annealed in a near isothermal hot wall chamber. By making use of the shallow penetration depth of UV light in silicon, we can distinguish Raman signals of single-crystalline, deficiently recrystallized, as well as amorphous silicon. Although, a clear, single crystalline lattice image was observed by transmission electron microscopy (TEM), the UV-Raman spectroscopy also sensitively detected deterioration of the lattice, but in nondestructive testing","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130094510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Non-Destructive Characterization of Metal-Semiconductor Interface by Raman Scattering 金属-半导体界面的拉曼散射无损表征
H. Harima
{"title":"Non-Destructive Characterization of Metal-Semiconductor Interface by Raman Scattering","authors":"H. Harima","doi":"10.1109/RTP.2006.367990","DOIUrl":"https://doi.org/10.1109/RTP.2006.367990","url":null,"abstract":"Raman scattering is a very powerful tool for micro- and nano-metric scale characterization of precise device manufacturing process in nondestructive and noncontact way. As an example, this paper describes interface interactions between metallic electrodes and Si characterized by Raman scattering","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127705301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Titanium Silicide Formation: Process Characterization Using Single Wafer Rapid Thermal Furnace System 硅化钛的形成:单晶片快速热炉系统的工艺表征
D. Garroux, M. Ouaknine, I. J. Malik, T. Fukada, M. Odera, T. Ishigaki, T. Ueda, W. Yoo
{"title":"Titanium Silicide Formation: Process Characterization Using Single Wafer Rapid Thermal Furnace System","authors":"D. Garroux, M. Ouaknine, I. J. Malik, T. Fukada, M. Odera, T. Ishigaki, T. Ueda, W. Yoo","doi":"10.1109/RTP.2006.368009","DOIUrl":"https://doi.org/10.1109/RTP.2006.368009","url":null,"abstract":"Formation of titanium silicide was studied using a \"hot wall\" single wafer rapid thermal furnace (SRTF) system. Average sheet resistance and uniformity of TiSi2 films before and after processing, as well as process repeatability were evaluated. We also collected data for annealing of implanted wafers, oxide thickness & uniformity before and after dry and wet oxidation. We use this data to demonstrate process repeatability for anneals in the SRTF system. Comparison with wafers processed with Altis Semiconductor tool of record (TOR) gave some useful information regarding differences between wafers processed in lamp-based RTA and SRTF systems","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Millisecond Annealing with Flashlamps: Tool and Process Challenges 闪光灯毫秒退火:工具和工艺挑战
T. Gebel, L. Rebohle, R. Fendler, W. Hentsch, W. Skorupa, M. Voelskow, W. Anwand, R. Yankov
{"title":"Millisecond Annealing with Flashlamps: Tool and Process Challenges","authors":"T. Gebel, L. Rebohle, R. Fendler, W. Hentsch, W. Skorupa, M. Voelskow, W. Anwand, R. Yankov","doi":"10.1109/RTP.2006.367981","DOIUrl":"https://doi.org/10.1109/RTP.2006.367981","url":null,"abstract":"Sub-second annealing is one of the key issues to meet the requirements of the 45 nm technology node according to the ITRS roadmap. Therefore, over the past decade there has been great interest in techniques such as laser and flash lamp annealing (FLA). In addition, advanced ultra-fast annealing shows promise for technologies that are not directly related to Si device processing. The main reason for using FLA in alternative applications is the reduced thermal budget because of the short annealing time, which enables one to achieve high temperatures (> 500degC) in the near-surface region while keeping the substrate bulk relatively cold. This is of particularly high importance for the development of novel polymer-based electronics and flexible solar cell technologies, where the substrates cannot withstand temperatures in excess of 150degC. An overview of theoretical simulations and related results from FLA experiments for a variety of layered systems is given. The influence of the flash duration and intensity on the heat distribution and the resulting physical properties is considered. Design and performance issues of the FLA tools depending on the specific uses and technical requirements are addressed. Furthermore, topics covered include high-throughput applications e.g. for roll-to-roll production of polymer substrates. Results of a prototype tool for multi-flash processing up to a frequency of 1 Hz using a pulse duration of 1 ms are also discussed","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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