Pattern Effects with the Mask off...

Abstract

Pattern effects during RTP have been extensively studied for the last 15 years, but have only recently attained focus in device production. The detection and the evaluation of pattern effects are in most cases difficult. Different coatings on the Si wafers hinder direct measurements and indirect evaluations. Production people recognize pattern effect frequently as a malfunction in temperature control. People in process integration can not easily separate the main root cause of broader parameter distribution in electrical parameters in final test due to the overlapping results of CD variations in lithography and those of the microloading effects in RTP, CMP and plasma etch processing. In this paper the authors clarify the versatile realisations of pattern effects in different geometrical fractals and for different coating materials. The authors describe new methods for easy evaluation of pattern effects in production. An inherent solution to eliminate pattern effects in dual side heated RTP is to create a (hot) black body cavity at the frontside of the production wafer. This can be achieved by positioning an additional Si wafer (called hot shield) near the frontside of the production wafer. This arrangement allows 150 K/s ramp rate and dramatically reduces intra-die variations compared to a process where a wafer is heated without the hot shield at the same ramp up rate. The enhanced thermal mass with the hot shield results in slightly longer "peak time" for spike annealing. The modelling results show that the actual longer peak time can easily be compensated by slightly reduced maximum temperature and by changed implant parameters