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2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors最新文献

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Flash Lamp Annealing Latest Technology for 45nm device and Future devices 45纳米器件及未来器件的闪光灯退火最新技术
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367983
H. Kiyama
{"title":"Flash Lamp Annealing Latest Technology for 45nm device and Future devices","authors":"H. Kiyama","doi":"10.1109/RTP.2006.367983","DOIUrl":"https://doi.org/10.1109/RTP.2006.367983","url":null,"abstract":"FLA (flash lamp annealing) is used in 65nm generation devices manufacturing. For next 45nm and future generation devices, we have picked up 3 key subjects related to milli-second annealing: process controllability, S/D (source drain) activation, silicidation. No need to say, process controllability is very important for device manufacturing. And process requirement for S/D activation and silicidation controllability is becoming more and more severe. Under evaluation of these subjects, it became clear that FLA technology is still a hopeful candidate for 45nm device and future","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116632814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimization of annealing for ClusterBoron® and ClusterCarbon PMOS SDE ClusterBoron®和ClusterCarbon PMOS SDE的退火优化
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.368008
K. Sekar, W. Krull, K. Verheyden, K. Funk
{"title":"Optimization of annealing for ClusterBoron® and ClusterCarbon PMOS SDE","authors":"K. Sekar, W. Krull, K. Verheyden, K. Funk","doi":"10.1109/RTP.2006.368008","DOIUrl":"https://doi.org/10.1109/RTP.2006.368008","url":null,"abstract":"High dopant activation and low implant damage are crucial in realizing the formation of a low resistivity ultra shallow junction (USJ). Future annealing process requires diffusion less activation and has ultimately define the junction depth. Conventional boron implant at ultra-low energies perform poorly in throughput and in energy contamination. Molecular species (B18H22) can provide implants with no energy contamination and low beam divergence along with self-amorphization. Implantation of ClusterBoron in combination with ClusterCarbon can provide junction depths in the 15-20 nm regime and achieve a higher level of dopant activation with conventional spike anneal. We used various ClusterBoron and ClusterCarbon energies and doses along with various anneal techniques to arrive at an optimum resistivity and junction depth for PMOS SDE applications. We carried out various analytical measurements like SIMS, sheet-resistance to understand the self-amorphization, enhanced dopant activation and the damage level effect of the dopants after the anneals. The results are discussed in detail in the paper","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121338651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Micro-Scale Sheet Resistance Measurements on Ultra Shallow Junctions 超浅结的微尺度薄片电阻测量
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367996
C. L. Petersen, R. Lin, D. H. Petersen, P. Nielsen
{"title":"Micro-Scale Sheet Resistance Measurements on Ultra Shallow Junctions","authors":"C. L. Petersen, R. Lin, D. H. Petersen, P. Nielsen","doi":"10.1109/RTP.2006.367996","DOIUrl":"https://doi.org/10.1109/RTP.2006.367996","url":null,"abstract":"The paper reports a new method for measuring sheet resistance on implanted wafers by using micro-fabricated four-point probes with a tip-to-tip spacing of a few microns. These microscopic probes have a contact force five orders of magnitude smaller than conventional probes, and can perform local non-destructive ultra shallow junction (USJ) sheet resistance measurements on both blanket and patterned wafers. The authors demonstrate this new technique on laser annealed wafers, measuring micro-scale sheet resistance variations on wafers that appear homogeneous when mapped with conventional four-point probes. The microscopic four-point probes detect stitching effects caused by laser spot overlap/misalignment during the annealing process. The findings indicate that such local sheet resistance in-homogeneities average out in conventional four-point measurements, and that new metrology is therefore needed to fully characterize USJ wafers activated by laser anneal and other diffusion-less methods","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114446974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies 90 NM和65 NM技术的脉冲、闪蒸和激光退火工艺集成问题
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367984
T. Feudel, M. Horstmann, L. Herrmann, M. Herden, M. Gerhardt, D. Greenlaw, P. Fisher, J. Kluth
{"title":"Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies","authors":"T. Feudel, M. Horstmann, L. Herrmann, M. Herden, M. Gerhardt, D. Greenlaw, P. Fisher, J. Kluth","doi":"10.1109/RTP.2006.367984","DOIUrl":"https://doi.org/10.1109/RTP.2006.367984","url":null,"abstract":"With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128103046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Flash Annealing Technology for USJ: Modeling and Metrology USJ闪蒸退火技术:建模与计量
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367988
J. Gelpey, S. Mccoy, D. Camm, W. Lerch, S. Paul, P. Pichler, J. Borland, P. Timans
{"title":"Flash Annealing Technology for USJ: Modeling and Metrology","authors":"J. Gelpey, S. Mccoy, D. Camm, W. Lerch, S. Paul, P. Pichler, J. Borland, P. Timans","doi":"10.1109/RTP.2006.367988","DOIUrl":"https://doi.org/10.1109/RTP.2006.367988","url":null,"abstract":"Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper provides an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128189021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low Thermal Budget Activation of B in Si B在Si中的低热收支活化
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.368001
H. Bourdon, A. Halimaoui, A. Talbot, J. Venturini, O. Marcelot, D. Dutartre
{"title":"Low Thermal Budget Activation of B in Si","authors":"H. Bourdon, A. Halimaoui, A. Talbot, J. Venturini, O. Marcelot, D. Dutartre","doi":"10.1109/RTP.2006.368001","DOIUrl":"https://doi.org/10.1109/RTP.2006.368001","url":null,"abstract":"Advanced devices may today require implantation and annealing steps after the metallic interconnection realization. Depending on the application, a thin p-doped layer has to be formed after wafer bonding. The issue, in such a case, is to correctly anneal the Boron implanted layer without degrading the buried devices and interconnections which lies at a depth around 3mum below the surface. Here, the authors propose to study different way to anneal this thin p-doped layer. Low energy and low dose implantations are performed without reaching the amorphisation threshold. Long thermal annealing at 400degC (RTP) and UV laser annealing are investigated through sheet resistance, thermal wave, SIMS or TEM. On one hand, a significant activation is obtained with RTP at temperature as low as 400degC and that Boron is activated with a better activation rate with B+ than with BF2 +. On the other hand, a much better activation was achieved with laser annealing as compared to RTP regardless of the implantation conditions","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Laser Annealing Technology and Device Integration Challenges 激光退火技术和器件集成挑战
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367976
A. Shima
{"title":"Laser Annealing Technology and Device Integration Challenges","authors":"A. Shima","doi":"10.1109/RTP.2006.367976","DOIUrl":"https://doi.org/10.1109/RTP.2006.367976","url":null,"abstract":"We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal process (LTP) was also investigated in conjunction with LSA S/D activation to effectively suppress poly-Si gate depletion while achieving highly activated ultra-shallow junctions in S/D, leading to improved transistor performance. Ioff was reduced more than one order of magnitude compared with conventional spike RTA devices","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"38 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125737834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Rapid Thermal Processing Strategies for Highly Uniform and Repeatable Process Results on Patterned Wafers 快速热处理策略对高均匀和可重复的过程结果的图案晶圆
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.367997
W. Yoo
{"title":"Rapid Thermal Processing Strategies for Highly Uniform and Repeatable Process Results on Patterned Wafers","authors":"W. Yoo","doi":"10.1109/RTP.2006.367997","DOIUrl":"https://doi.org/10.1109/RTP.2006.367997","url":null,"abstract":"Advantages and disadvantages of various types of temperature measurement techniques are reviewed in terms of potential temperature measurement errors and their impact on process consistency. Direct wafer temperature control and indirect wafer temperature control through control of the wafer environment are compared from the viewpoints of process accuracy and repeatability. The origin of both intrinsic and extrinsic pattern effects is identified and its impact on thermal non-uniformities in various wafer heating environments is analyzed. Based on the analysis, effective RTP strategies for highly uniform and repeatable process results on patterned wafers are proposed and discussed","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"30 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125860909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Insertion Error in LPRT Temperature Measurements LPRT温度测量中的插入误差
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.368012
Y. Qu, E. Puttitwong, J. Howell, O. Ezekoye
{"title":"Insertion Error in LPRT Temperature Measurements","authors":"Y. Qu, E. Puttitwong, J. Howell, O. Ezekoye","doi":"10.1109/RTP.2006.368012","DOIUrl":"https://doi.org/10.1109/RTP.2006.368012","url":null,"abstract":"Accurate measurement of surface temperature distribution is of great concern in the semiconductor industries, particularly in rapid thermal processing (RTP). The International Technology Roadmap for Semiconductors 2004 (ITRS) has established requirements of uncertainties of plusmn1.5 degC at temperature of 1000 degC, with temperature calibration traceable to ITS-90 (International Temperature Scale-1990). Light-pipe radiation thermometers (LPRTs) are becoming increasingly important as an industrial tool for temperature measurement, especially in the semiconductor industry. However, there are several radiation issues associate with LPRTs, and without fully understanding them, achieving further accuracy could be hobbled. In this paper, we concentrate on the insertion error in the LPRTs temperature measurement. The \"drawdown effect\" and \"shadow effect\" are investigated. The \"drawdown effect\" is caused by the physical mass of the light-pipe probe acting as a heat sink for the measured object and the \"shadow effect\" is caused by distortion of radiosity due to the presence of the light-pipe probe. Monte Carlo simulation was conducted and compared to the experiment results","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133284765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Raman Study on the Process of SI Advanced Integrated Circuits SI先进集成电路过程的拉曼研究
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors Pub Date : 2006-10-01 DOI: 10.1109/RTP.2006.368002
S. Nishibe, T. Sasaki, H. Harima, K. Kisoda, T. Yamazaki, W. Yoo
{"title":"Raman Study on the Process of SI Advanced Integrated Circuits","authors":"S. Nishibe, T. Sasaki, H. Harima, K. Kisoda, T. Yamazaki, W. Yoo","doi":"10.1109/RTP.2006.368002","DOIUrl":"https://doi.org/10.1109/RTP.2006.368002","url":null,"abstract":"Precise control of fabrication processing is a key point for future integration technology of Si devices. Reliable characterization of Si wafers at each fabrication process is indispensable. Raman scattering has high-potential as a technique for noncontact and nondestructive characterization which yields valuable information on Si-based materials. Here, a patterned Si wafer for a modern electronic device is characterized by Raman microprobe to study the effect of different processes on residual stress, as well as other physical aspects","PeriodicalId":114586,"journal":{"name":"2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"34 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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